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تسجيل مستخدم جديدQuantum Annealing Correction with Minor Embedding
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Quantum annealing provides a promising route for the development of quantum optimization devices, but the usefulness of such devices will be limited in part by the range of implementable problems as dictated by hardware constraints. To overcome constraints imposed by restricted connectivity between qubits, a larger set of interactions can be approximated using minor embedding techniques whereby several physical qubits are used to represent a single logical qubit. However, minor embedding introduces new types of errors due to its approximate nature. We introduce and study quantum annealing correction schemes designed to improve the performance of quantum annealers in conjunction with minor embedding, thus leading to a hybrid scheme defined over an encoded graph. We argue that this scheme can be efficiently decoded using an energy minimization technique provided the density of errors does not exceed the per-site percolation threshold of the encoded graph. We test the hybrid scheme using a D-Wave Two processor on problems for which the encoded graph is a 2-level grid and the Ising model is known to be NP-hard. The problems we consider are frustrated Ising model problem instances with planted (a priori known) solutions. Applied in conjunction with optimized energy penalties and decoding techniques, we find that this approach enables the quantum annealer to solve minor embedded instances with significantly higher success probability than it would without error correction. Our work demonstrates that quantum annealing correction can and should be used to improve the robustness of quantum annealing not only for natively embeddable problems, but also when minor embedding is used to extend the connectivity of physical devices.
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A significant challenge in quantum annealing is to map a real-world problem onto a hardware graph of limited connectivity. If the maximum degree of the problem graph exceeds the maximum degree of the hardware graph, one employs minor embedding in whi
ch each logical qubit is mapped to a tree of physical qubits. Pairwise interactions between physical qubits in the tree are set to be ferromagnetic with some coupling strength $F<0$. Here we address the question of what value $F$ should take in order to maximise the probability that the annealer finds the correct ground-state of an Ising problem. The sum of $|F|$ for each logical qubit is defined as minor embedding energy. We confirm experimentally that the ground-state probability is maximised when the minor embedding energy is minimised, subject to the constraint that no domain walls appear in every tree of physical qubits associated with each embedded logical qubit. We further develop an analytical lower bound on $|F|$ which satisfies this constraint and show that it is a tighter bound than that previously derived by Choi (Quantum Inf. Proc. 7 193 (2008)).
We present a general error-correcting scheme for quantum annealing that allows for the encoding of a logical qubit into an arbitrarily large number of physical qubits. Given any Ising model optimization problem, the encoding replaces each logical qub
it by a complete graph of degree $C$, representing the distance of the error-correcting code. A subsequent minor-embedding step then implements the encoding on the underlying hardware graph of the quantum annealer. We demonstrate experimentally that the performance of a D-Wave Two quantum annealing device improves as $C$ grows. We show that the performance improvement can be interpreted as arising from an effective increase in the energy scale of the problem Hamiltonian, or equivalently, an effective reduction in the temperature at which the device operates. The number $C$ thus allows us to control the amount of protection against thermal and control errors, and in particular, to trade qubits for a lower effective temperature that scales as $C^{-eta}$, with $eta leq 2$. This effective temperature reduction is an important step towards scalable quantum annealing.
A major limitation of current generations of quantum annealers is the sparse connectivity of manufactured qubits in the hardware graph. This technological limitation generated considerable interest, motivating efforts to design efficient and adroit m
inor-embedding procedures that bypass sparsity constraints. In this paper, starting from a previous equational formulation by Dridi et al. (arXiv:1810.01440), we propose integer programming (IP) techniques for solving the minor-embedding problem. The first approach involves a direct translation from the previous equational formulation to IP, while the second decomposes the problem into an assignment master problem and fiber condition checking subproblems. The proposed methods are able to detect instance infeasibility and provide bounds on solution quality, capabilities not offered by currently employed heuristic methods. We demonstrate the efficacy of our methods with an extensive computational assessment involving three different families of random graphs of varying sizes and densities. The direct translation as a monolithic IP model can be solved with existing commercial solvers yielding valid minor-embeddings, however, is outperformed overall by the decomposition approach. Our results demonstrate the promise of our methods for the studied benchmarks, highlighting the advantages of using IP technology for minor-embedding problems.
In order to treat all-to-all connected quadratic binary optimization problems (QUBO) with hardware quantum annealers, an embedding of the original problem is required due to the sparsity of the hardwares topology. Embedding fully-connected graphs --
typically found in industrial applications -- incurs a quadratic space overhead and thus a significant overhead in the time to solution. Here we investigate this embedding penalty of established planar embedding schemes such as minor embedding on a square lattice, minor embedding on a Chimera graph, and the Lechner-Hauke-Zoller scheme using simulated quantum annealing on classical hardware. Large-scale quantum Monte Carlo simulation suggest a polynomial time-to-solution overhead. Our results demonstrate that standard analog quantum annealing hardware is at a disadvantage in comparison to classical digital annealers, as well as gate-model quantum annealers and could also serve as benchmark for improvements of the standard quantum annealing protocol.
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e required to ensure full scalability of quantum annealing. Quantum annealing correction (QAC) is a method that aims to improve the performance of quantum annealers when control over only the problem (final) Hamiltonian is possible, along with decoding. Building on our earlier work [S. Matsuura et al., Phys. Rev. Lett. 116, 220501 (2016)], we study QAC using analytical tools of statistical physics by considering the effects of temperature and a transverse field on the penalty qubits in the ferromagnetic $p$-body infinite-range transverse-field Ising model. We analyze the effect of QAC on second ($p=2$) and first ($pgeq 3$) order phase transitions, and construct the phase diagram as a function of temperature and penalty strength. Our analysis reveals that for sufficiently low temperatures and in the absence of a transverse field on the penalty qubit, QAC breaks up a single, large free energy barrier into multiple smaller ones. We find theoretical evidence for an optimal penalty strength in the case of a transverse field on the penalty qubit, a feature observed in QAC experiments. Our results provide further compelling evidence that QAC provides an advantage over unencoded quantum annealing.
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