اشترك بالحزمة الذهبية واحصل على وصول غير محدود شمرا أكاديميا
تسجيل مستخدم جديدTrack reconstruction in the emulsion-lead target of the OPERA experiment using the ESS microscope
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The OPERA experiment, designed to conclusively prove the existence of $rm u_mu to u_tau$ oscillations in the atmospheric sector, makes use of a massive lead-nuclear emulsion target to observe the appearance of $rm u_tau$s in the CNGS $rm u_mu$ beam. The location and analysis of the neutrino interactions in quasi real-time required the development of fast computer-controlled microscopes able to reconstruct particle tracks with sub-micron precision and high efficiency at a speed of 20 cm^2 / h. This paper describes the performance in particle track reconstruction of the European Scanning System, a novel automatic microscope for the measurement of emulsion films developed for OPERA.
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The main task of the Target Tracker detector of the long baseline neutrino oscillation OPERA experiment is to locate in which of the target elementary constituents, the lead/emulsion bricks, the neutrino interactions have occurred and also to give ca
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The OPERA experiment aims at measuring the u_{mu} -> u_{tau} oscillation through the u_{tau} appearance in an almost pure u_{mu} beam (CNGS). For the direct identification of the short-lived {tau} lepton, produced in u_{tau} CC interactions, a m
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The functions of the Low-Level Radio Frequency (LLRF) system at European Spallation Source (ESS) are implemented on different Field-Programmable Gate Array (FPGA) boards in a Micro Telecommunications Computing Architecture (MTCA) crate. Besides the a
lgorithm, code that provides access to the peripherals connected to the FPGA is necessary. In order to provide a common platform for the FPGA developments at ESS - the ESS FPGA Framework has been designed. The framework facilitates the integration of different algorithms on different FPGA boards. Three functions are provided by the framework: (1) Communication interfaces to peripherals, e.g. Analog-to-Digital Converters (ADCs) and on-board memory, (2) Upstream communication with the control system over Peripheral Component Interconnect Express (PCIe), and (3) Configuration of the on-board peripherals. To keep the framework easily extensible by Intellectual Property (IP) blocks and to enable seamless integration with the Xilinx design tools, the Advanced eXtensible Interface version 4 (AXI4) bus is the chosen communication interconnect. Furthermore, scripts automatize the building of the FPGA configuration, software components and the documentation. The LLRF control algorithms have been successfully integrated into the framework.
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