This work reports a compact behavioral model for gated-synaptic memory. The model is developed in Verilog-A for easy integration into computer-aided design of neuromorphic circuits using emerging memory. The model encompasses various forms of gated s
ynapses within a single framework and is not restricted to only a single type. The behavioral theory of the model is described in detail along with a full list of the default parameter settings. The model includes parameters such as a devices ideal set time, threshold voltage, general evolution of the conductance with respect to time, decay of the devices state, etc. Finally, the models validity is shown via extensive simulation and fitting to experimentally reported data on published gated-synapses.
Hardware security has risen in prominence in recent years with concerns stemming from a globalizing semiconductor supply chain and increased third-party IP (intellectual property) usage. Trojan detection is of paramount importance for ensuring system
s with confidentiality, integrity, and availability. Existing methods for hardware Trojan detection in FPGA (field programmable gate array) devices include test-time methods, pre-implementation methods, and run-time methods. The first two methods provide effective ways of detecting some Trojans; however, Trojans may be specifically designed to avoid detection at test-time or before implementation making run-time detection a more attractive option. Run-time detection and removal of Trojans is highly desirable due to the wide range of critical systems which are deployed on FPGAs and may be difficult or costly to remove from operation. Many parallels can be drawn between hardware and natural systems, and one example creates an analogy between hardware attacks and biological attacks. We propose a CRISPR-Cas-inspired (clustered regularly interspaced palindromic repeats) method for detecting hardware Trojans in FPGAs. The fundamental concepts of the Type 1-E CRISPR-Cas mechanism are discussed and simulated to predict the flow of genetic information through this biological system. The basic structure of this system is utilized to propose a novel run-time Trojan detection method titled CADEFT (CRISPR-Cas-based Algorithm for DEtection of FPGA Trojans). Different levels of FPGA application design flow are explored, and CADEFT is proposed for realization at the bitstream level to monitor the configuration bitstream and the run-time properties of the FPGA. The flexibility of CADEFT originates in the CRISPR-Cas mechanisms ability to recognize similar albeit previously unseen patterns which may pose a threat to the system.
