Controlled epitaxial graphene growth within amorphous carbon corrals

Structured growth of high quality graphene is necessary for technological development of carbon based electronics. Specifically, control of the bunching and placement of surface steps under epitaxial graphene on SiC is an important consideration for graphene device production. We demonstrate lithographically patterned evaporated amorphous carbon corrals as a method to pin SiC surface steps. Evaporated amorphous carbon is an ideal step-flow barrier on SiC due to its chemical compatibility with graphene growth and its structural stability at high temperatures, as well as its patternability. The amorphous carbon is deposited in vacuum on SiC prior to graphene growth. In the graphene furnace at temperatures above 1200$^circ$C, mobile SiC steps accumulate at these amorphous carbon barriers, forming an aligned step free region for graphene growth at temperatures above 1330$^circ$C. AFM imaging and Raman spectroscopy support the formation of quality step-free graphene sheets grown on SiC with the step morphology aligned to the carbon grid.

Wafer bonding solution to epitaxial graphene - silicon integration

The development of graphene electronics requires the integration of graphene devices with Si-CMOS technology. Most strategies involve the transfer of graphene sheets onto silicon, with the inherent difficulties of clean transfer and subsequent graphene nano-patterning that degrades considerably the electronic mobility of nanopatterned graphene. Epitaxial graphene (EG) by contrast is grown on an essentially perfect crystalline (semi-insulating) surface, and graphene nanostructures with exceptional properties have been realized by a selective growth process on tailored SiC surface that requires no graphene patterning. However, the temperatures required in this structured growth process are too high for silicon technology. Here we demonstrate a new graphene to Si integration strategy, with a bonded and interconnected compact double-wafer structure. Using silicon-on-insulator technology (SOI) a thin monocrystalline silicon layer ready for CMOS processing is applied on top of epitaxial graphene on SiC. The parallel Si and graphene platforms are interconnected by metal vias. This method inspired by the industrial development of 3d hyper-integration stacking thin-film electronic devices preserves the advantages of epitaxial graphene and enables the full spectrum of CMOS processing.

Scalable control of graphene growth on 4H-SiC C-face using decomposing silicon nitride masks

Patterning of graphene is key for device fabrication. We report a way to increase or reduce the number of layers in epitaxial graphene grown on the C-face (000-1) of silicon carbide by the deposition of a 120 nm to 150nm-thick silicon nitride (SiN) mask prior to graphitization. In this process we find that areas covered by a Si-rich SiN mask have one to four more layers than non-masked areas. Conversely N-rich SiN decreases the thickness by three layers. In both cases the mask decomposes before graphitization is completed. Graphene grown in masked areas show good quality as observed by Raman spectroscopy, atomic force microscopy (AFM) and transport data. By tailoring the growth parameters selective graphene growth and sub-micron patterns have been obtained.

A method to extract pure Raman spectrum of epitaxial graphene on SiC

A method is proposed to extract pure Raman spectrum of epitaxial graphene on SiC by using a Non-negative Matrix Factorization. It overcomes problems of negative spectral intensity and poorly resolved spectra resulting from a simple subtraction of a SiC background from the experimental data. We also show that the method is similar to deconvolution, for spectra composed of multiple sub- micrometer areas, with the advantage that no prior information on the impulse response functions is needed. We have used this property to characterize the Raman laser beam. The method capability in efficient data smoothing is also demonstrated.