Quantum dot (QD) lay-outs are becoming more complex as the technology is being applied to more complex multi-QD structures. This increase in complexity requires improved capacitance modeling both for design and accurate interpretation of QD propertie
s from measurement. A combination of process simulation, electrostatic simulation, and computer assisted design (CAD) lay-out packages are used to develop a three dimensional (3D) classical capacitance model. The agreement of the capacitances of the classical model is tested against two different, experimentally measured, topographically complex silicon QD geometries. Agreement with experiment, within 10-20%, is demonstrated for the two structures when the details of the structure are transferred from the CAD to the model capturing the full 3D topography. Small uncertainty in device dimensions due to uncontrolled variation in processing, like layer thickness and gate size, are calculated to be sufficient to explain the disagreement. The sensitivity of the capacitances to small variations in the structure also highlights the limits of accuracy of capacitance models for QD analysis. We furthermore observe that a critical density, the metal insulator transition, can be used as a good approximation of the metallic edge of the quantum dot when electron density in the dot is calculated directly with a semi-classical simulation.
