Miniaturizing transmon qubits using van der Waals materials

Quantum computers can potentially achieve an exponential speedup versus classical computers on certain computational tasks, as recently demonstrated in systems of superconducting qubits. However, these qubits have large footprints due to their large capacitor electrodes needed to suppress losses by avoiding dielectric materials. This tactic hinders scaling by increasing parasitic coupling among circuit components, degrading individual qubit addressability, and limiting the spatial density of qubits. Here, we take advantage of the unique properties of the van der Waals (vdW) materials to reduce the qubit area by a factor of $>1000$ while preserving the required capacitance without increasing substantial loss. Our qubits combine conventional aluminum-based Josephson junctions with parallel-plate capacitors composed of crystalline layers of superconducting niobium diselenide (NbSe$_2$) and insulating hexagonal-boron nitride (hBN). We measure a vdW transmon $T_1$ relaxation time of 1.06 $mu$s, which demonstrates a path to achieve high-qubit-density quantum processors with long coherence times, and illustrates the broad utility of layered heterostructures in low-loss, high-coherence quantum devices.

Characterizing mid-circuit measurements on a superconducting qubit using gate set tomography

Measurements that occur within the internal layers of a quantum circuit -- mid-circuit measurements -- are an important quantum computing primitive, most notably for quantum error correction. Mid-circuit measurements have both classical and quantum outputs, so they can be subject to error modes that do not exist for measurements that terminate quantum circuits. Here we show how to characterize mid-circuit measurements, modelled by quantum instruments, using a technique that we call quantum instrument linear gate set tomography (QILGST). We then apply this technique to characterize a dispersive measurement on a superconducting transmon qubit within a multiqubit system. By varying the delay time between the measurement pulse and subsequent gates, we explore the impact of residual cavity photon population on measurement error. QILGST can resolve different error modes and quantify the total error from a measurement; in our experiment, for delay times above 1000 ns we measured a total error rate (i.e., half diamond distance) of $epsilon_{diamond} = 8.1 pm 1.4 %$, a readout fidelity of $97.0 pm 0.3%$, and output quantum state fidelities of $96.7 pm 0.6%$ and $93.7 pm 0.7%$ when measuring $0$ and $1$, respectively.

Reservoir Computing with Superconducting Electronics

The rapidity and low power consumption of superconducting electronics makes them an ideal substrate for physical reservoir computing, which commandeers the computational power inherent to the evolution of a dynamical system for the purposes of performing machine learning tasks. We focus on a subset of superconducting circuits that exhibit soliton-like dynamics in simple transmission line geometries. With numerical simulations we demonstrate the effectiveness of these circuits in performing higher-order parity calculations and channel equalization at rates approaching 100 Gb/s. The availability of a proven superconducting logic scheme considerably simplifies the path to a fully integrated reservoir computing platform and makes superconducting reservoirs an enticing substrate for high rate signal processing applications.

Cryogenic Memory Architecture Integrating Spin Hall Effect based Magnetic Memory and Superconductive Cryotron Devices

One of the most challenging obstacles to realizing exascale computing is minimizing the energy consumption of L2 cache, main memory, and interconnects to that memory. For promising cryogenic computing schemes utilizing Josephson junction superconducting logic, this obstacle is exacerbated by the cryogenic system requirements that expose the technologys lack of high-density, high-speed and power-efficient memory. Here we demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below $10^{-6}$, and a 4x4 array can be fully addressed with bit select error rates of $10^{-6}$. This demonstration is a first step towards a full cryogenic memory architecture targeting energy and performance specifications appropriate for applications in superconducting high performance and quantum computing control systems, which require significant memory resources operating at 4 K.