We present the first study of the intrinsic electrical properties of WS$_2$ transistors fabricated with two different dielectric environments WS$_2$ on SiO$_2$ and WS$_2$ on h-BN/SiO$_2$, respectively. A comparative analysis of the electrical charact
eristics of multiple transistors fabricated from natural and synthetic WS$_2$ with various thicknesses from single- up to four-layers and over a wide temperature range from 300K down to 4.2 K shows that disorder intrinsic to WS$_2$ is currently the limiting factor of the electrical properties of this material. These results shed light on the role played by extrinsic factors such as charge traps in the oxide dielectric thought to be the cause for the commonly observed small values of charge carrier mobility in transition metal dichalcogenides.
We present a fabrication process for high quality suspended and double gated trilayer graphene devices. The electrical transport measurements in these transistors reveal a high charge carrier mobility (higher than 20000 cm^2/Vs) and ballistic electri
c transport on a scale larger than 200nm. We report a particularly large on/off ratio of the current in ABC-stacked trilayers, up to 250 for an average electric displacement of -0.08 V/nm, compatible with an electric field induced energy gap. The high quality of these devices is also demonstrated by the appearance of quantum Hall plateaus at magnetic fields as low as 500mT.
