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Register a new userOn the suitability of hBN as an insulator for 2D material-based ultrascaled CMOS devices
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Complementary metal oxide semiconductor (CMOS) logic circuits at the ultimate scaling limit place the utmost demands on the properties of all materials involved. The requirements for semiconductors are well explored and could possibly be satisfied by a number of layered two-dimensional (2D) materials, like for example transition-metal dichalcogenides or black phosphorus. The requirements for the gate insulator are arguably even more challenging and difficult to meet. In particular the combination of insulator to semiconductor which forms the central element of the metal oxide semiconductor field effect transistor (MOSFET) has to be of superior quality in order to build competitive devices. At the moment, hexagonal boron nitride (hBN) is the most common two-dimensional insulator and widely considered to be the most promising gate insulator in nanoscaled 2D material-based transistors. Here, we critically assess the material parameters of hBN and conclude that while its properties render hBN an ideal candidate for many applications in 2D nanoelectronics, hBN is most likely not suitable as a gate insulator for ultrascaled CMOS devices.
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Developing novel techniques for depositing transition metal dichalcogenides is crucial for the industrial adoption of 2D materials in optoelectronics. In this work, the lateral growth of molybdenum disulfide (MoS2) over an insulating surface is demonstrated using electrochemical deposition. By fabricating a new type of microelectrodes, MoS2 2D films grown from TiN electrodes across opposite sides have been connected over an insulating substrate, hence, forming a lateral device structure through only one lithography and deposition step. Using a variety of characterization techniques, the growth rate of MoS2 has been shown to be highly anisotropic with lateral to vertical growth ratios exceeding 20-fold. Electronic and photo-response measurements on the device structures demonstrate that the electrodeposited MoS2 layers behave like semiconductors, confirming their potential for photodetection applications. This lateral growth technique paves the way towards room temperature, scalable and site-selective production of various transition metal dichalcogenides and their lateral heterostructures for 2D materials-based fabricated devices.
The unique properties and atomic thickness of two-dimensional (2D) materials enable smaller and better nanoelectromechanical sensors with novel functionalities. During the last decade, many studies have successfully shown the feasibility of using suspended membranes of 2D materials in pressure sensors, microphones, accelerometers, and mass and gas sensors. In this review, we explain the different sensing concepts and give an overview of the relevant material properties, fabrication routes, and device operation principles. Finally, we discuss sensor readout and integration methods and provide comparisons against the state of the art to show both the challenges and promises of 2D material-based nanoelectromechanical sensing.
In 1963, Moll and Tarui suggested that the field-effect conductance of a semiconductor could be controlled by the remanent polarization of a ferroelectric (FE) material to create a ferroelectric field-effect transistor (FE-FET). However, subsequent efforts to produce a practical, compact FE-FET have been plagued by low retention and incompatibility with Complementary Metal Oxide Semiconductor (CMOS) process integration. These difficulties led to the development of trapped-charge based memory devices (also called floating gate or flash memory), and these are now the mainstream non-volatile memory (NVM) technology. Over the past two decades, advances in oxide FE materials have rejuvenated the field of ferroelectrics and made FE random access memories (FE-RAM) a commercial reality. Despite these advances, commercial FE-RAM based on lead zirconium titanate (PZT) has stalled at the 130 nm due to process challenges.The recent discovery of scandium doped aluminum nitride (AlScN) as a CMOS compatible ferroelectric presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approx. 350 C). This temperature is compatible with CMOS back end of line processes. Here, we present a FE-FET device composed of an AlScN FE dielectric layer integrated with a channel layer of a van der Waals two-dimensional (2D) semiconductor, MoS2. Our devices show an ON/OFF ratio ~ 10^6, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable, two-state memory retention for up to 10^4 seconds. Our simulations and experimental results suggest that the combination of AlScN and 2D semiconductors is nearly ideal for low power FE-FET memory. These results demonstrate a new approach in embedded memory and in-memory computing, and could even lead to effective neuromorphic computing architectures.
Light-matter interaction with two-dimensional materials gained significant attention in recent years leading to the reporting of weak and strong coupling regimes, and effective nano-laser operation with various structures. Particularly, future applications involving monolayer materials in waveguide-coupled on-chip integrated circuitry and valleytronic nanophotonics require controlling, directing and optimizing photoluminescence. In this context, photoluminescence enhancement from monolayer transition-metal dichalcogenides on patterned semiconducting substrates becomes attractive. It is demonstrated in our work using focussed-ion-beam-etched GaP and monolayer WS2 suspended on hexagonal-BN buffer sheets. We present a unique optical microcavity approach capable of both efficient in-plane and out-of-plane confinement of light, which results in a WS2 photoluminescence enhancement by a factor of 10 compared to the unstructured substrate at room temperature. The key concept is the combination of interference effects in both the horizontal direction using a bulls-eye-shaped circular Bragg grating and in vertical direction by means of a multiple reflection model with optimized etch depth of circular air-GaP structures for maximum constructive interference effects of the applied pump and expected emission light.
The microelectronics industry is pushing the fundamental limit on the physical size of individual elements to produce faster and more powerful integrated chips. These chips have nanoscale features that dissipate power resulting in nanoscale hotspots leading to device failures. To understand the reliability impact of the hotspots, the device needs to be tested under the actual operating conditions. Therefore, the development of high-resolution thermometry techniques is required to understand the heat dissipation processes during the device operation. Recently, several thermometry techniques have been proposed,such as radiation thermometry, thermocouple based contact thermometry, scanning thermal microscopy (SThM), scanning transmission electron microscopy (STEM) and transition based threshold thermometers. However, most of these techniques have limitations including the need for extensive calibration, perturbation of the actual device temperature, low throughput, and the use of ultra-high vacuum. Here, we present a facile technique, which uses a thin film contact thermometer based on the phase change material Ge2Sb2Te5, to precisely map thermal contours from the nanoscale to the microscale. Ge2Sb2Te5 undergoes a crystalline transition at Tg with large changes in its electric conductivity, optical reflectivity and density. Using this approach, we map the surface temperature of a nanowire and an embedded micro-heater on the same chip where the scales of the temperature contours differ by three orders of magnitude. The spatial resolution can be as high as 20 nanometers thanks to the continuous nature of the thin film.
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