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Register a new userCryogenic Characerization and Modeling of Standard CMOS down to Liquid Helium Temperature for Quantum Computing
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Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias conditions at temperatures ranging from 300K down to 4.2K. We extracted their fundamental physical parameters and developed a compact model based on BSIM3V3. In addition to their I-V characteristics, threshold voltage(Vth) values, on/off current ratio, transconductance of the MOS transistors, and resistors on chips are measured at temperatures from 300K down to 4.2K. A simple subcircuit was built to correct the kink effect. This work provides experimental evidence for implementation of cryogenic CMOS technology, a valid industrial tape-out process model, and romotes the application of integrated circuits in cryogenic environments, including quantum measurement and control systems for quantum chips at very low temperatures.
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In this paper a commercial 28-nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry-standard compact models to cryogenic temperatures for the design of cryo- CMOS circuits implemented in a 28 nm FDSOI technology.
Previous cryogenic electronics studies are most above 4.2K. In this paper we present the cryogenic characterization of a 0.18{mu}m standard bulk CMOS technology(1.8V and 5V) at sub-kelvin temperature around 270mK. PMOS and NMOS devices with different width to length ratios(W/L) are tested and characterized under various bias conditions at temperatures from 300K to 270mK. It is shown that the 0.18{mu}m standard bulk CMOS technology is still working at sub-kelvin temperature. The kink effect and current overshoot phenomenon are observed at sub-kelvin temperature. Especially, current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of large and thin-oxide devices at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.
This paper presents low power dissipation, low phase noise ring oscillators (ROs) based on Semiconductor Manufacturing International Corporation (SMIC) 0.18{mu}m CMOS technology at liquid helium temperature (LHT). First, the characterization and modelling of CMOS at LHT are presented. The temperature-dependent device parameters are revised and the model then shows good agreement with the measurement results. The ring oscillator is then designed with energy efficiency optimization by application of forward body biasing (FBB). FBB is proposed to compensate for the threshold voltage (VTH) shift to preserve the benefits of the enhancement of the carrier mobility at 4.2K. The delay per stage ({tau}p), the static current (ISTAT), the dynamic current (IDYN), the power dissipation (P) and the phase noise (L(foff)) are analyzed at both 298 K and 4.2 K, with and without FBB. The performance of the designed RO in terms of speed ({tau}p=179ps), static current (23.55nA/stage), power dissipation (2.13{mu}W) and phase noise (-177.57dBc/Hz@1MHz) can be achieved at 4.2K with the supply voltage (VDD) reduced to 0.9V.
This paper reports the first cryogenic characterization of 28nm Fully-Depleted-SOI CMOS technology. A comprehensive study of digital/analog performances and body-biasing from room to the liquid helium temperature is presented. Despite a cryogenic operation, effectiveness of body-biasing remains unchanged and provides an excellent $V_{TH}$ controllability. Low-temperature operation enables higher drive current and a largely reduced subthreshold swing (down to 7mV/dec). FDSOI can provide a valuable approach to cryogenic low-power electronics. Applications such as classical control hardware for quantum processors are envisioned.
This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2,K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4,K and 4.2,K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77,K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.
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