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Register a new userRobust Mode Space Approach for Atomistic Modeling of Realistically Large Nanowire Transistors
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Atomistic quantum transport simulation of realistically large devices is computationally very demanding. The widely used mode space (MS) approach can significantly reduce the numerical cost but good MS basis is usually very hard to obtain for atomistic full-band models. In this work, a robust and parallel algorithm is developed to optimize the MS basis for atomistic nanowires. This enables tight binding non-equilibrium Greens function (NEGF) simulation of nanowire MOSFET with realistic cross section of $rm 10nmtimes10nm$ using a small computer cluster. This approach is applied to compare the performance of InGaAs and Si nanowire nMOSFETs with various channel lengths and cross sections. Simulation results with full-band accuracy indicate that InGaAs nanowire nMOSFETs have no drive current advantage over their Si counterparts for cross sections up to about $rm 10nmtimes10nm$.
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The ballistic performance of electron transport in nanowire transistors is examined using a 10 orbital sp3d5s* atomistic tight-binding model for the description of the electronic structure, and the top-of-the-barrier semiclassical ballistic model for calculation of the transport properties of the transistors. The dispersion is self consistently computed with a 2D Poisson solution for the electrostatic potential in the cross section of the wire. The effective mass of the nanowire changes significantly from the bulk value under strong quantization, and effects such as valley splitting strongly lift the degeneracies of the valleys. These effects are pronounced even further under filling of the lattice with charge. The effective mass approximation is in good agreement with the tight binding model in terms of current-voltage characteristics only in certain cases. In general, for small diameter wires, the effective mass approximation fails.
We have developed an efficient scalable kernel method for thermal transport in open systems, with which we have computed the thermal conductance of a junction between bulk silicon and silicon nanowires with diameter up to 10 nm. We have devised scaling laws for transmission and reflection spectra, which allow us to predict the thermal resistance of bulk-nanowire interfaces with larger cross sections than those achievable with atomistic simulations. Our results indicate the characteristic size beyond which atomistic systems can be treated accurately by mesoscopic theories.
The Cooper-pair transistor (CPT), a small superconducting island enclosed between two Josephson weak links, is the atomic building block of various superconducting quantum circuits. Utilizing gate-tunable semiconductor channels as weak links, the energy scale associated with the Josephson tunneling can be changed with respect to the charging energy of the island, tuning the extent of its charge fluctuations. Here, we directly demonstrate this control by mapping the energy level structure of a CPT made of an indium arsenide nanowire (NW) with a superconducting aluminum shell. We extract the device parameters based on the exhaustive modeling of the quantum dynamics of the phase-biased nanowire CPT and directly measure the even-odd parity occupation ratio as a function of the device temperature, relevant for superconducting and prospective topological qubits.
We report the operation of a field-effect transistor based on a single InAs nanowire gated by an ionic liquid. Liquid gating yields very efficient carrier modulation with a transconductance value thirty time larger than standard back gating with the SiO2 /Si++ substrate. Thanks to this wide modulation we show the controlled evolution from semiconductor to metallic-like behavior in the nanowire. This work provides the first systematic study of ionic-liquid gating in electronic devices based on individual III-V semiconductor nanowires: we argue this architecture opens the way to a wide range of fundamental and applied studies from the phase-transitions to bioelectronics.
We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favourable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.
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