No Arabic abstract
Investigation of HV-CMOS sensors for use as a tracking detector in the ATLAS experiment at the upgraded LHC (HL-LHC) has recently been an active field of research. A potential candidate for a pixel detector built in Silicon-On-Insulator (SOI) technology has already been characterized in terms of radiation hardness to TID (Total Ionizing Dose) and charge collection after a moderate neutron irradiation. In this article we present results of an extensive irradiation hardness study with neutrons up to a fluence of 1x10e16 neq/cm2. Charge collection in a passive pixelated structure was measured by Edge Transient Current Technique (E-TCT). The evolution of the effective space charge concentration was found to be compliant with the acceptor removal model, with the minimum of the space charge concentration being reached after 5x10e14 neq/cm2. An investigation of the in-pixel uniformity of the detector response revealed parasitic charge collection by the epitaxial silicon layer characteristic for the SOI design. The results were backed by a numerical simulation of charge collection in an equivalent detector layout.
An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffer from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry witch mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.
Edge-TCT and charge collection measurements with passive test structures made in LFoundry 150 nm CMOS process on p-type substrate with initial resistivity of over 3 k$Omega$cm are presented. Measurements were made before and after irradiation with reactor neutrons up to 2$cdot$10$^{15}$ n$_{mathrm{eq}}$/cm$^2$. Two sets of devices were investigated: unthinned (700 $mu$m) with substrate biased through the implant on top and thinned (200 $mu$m) with processed and metallised back plane. Depleted depth was estimated with Edge-TCT and collected charge was measured with $^{90}$Sr source using an external amplifier with 25 ns shaping time. Depleted depth at given bias voltage decreased with increasing neutron fluence but it was still larger than 70 $mu$m at 250 V after the highest fluence. After irradiation much higher collected charge was measured with thinned detectors with processed back plane although the same depleted depth was observed with Edge-TCT. Most probable value of collected charge of over 5000 electrons was measured also after irradiation to 2$cdot$10$^{15}$ n$_{mathrm{eq}}$/cm$^2$. This is sufficient to ensure successful operation of these detectors at the outer layer of the pixel detector in the ATLAS experiment at the upgraded HL-LHC.
HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the $4^{mathrm{th}}$ generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between $1cdot 10^{14}$ and $5cdot 10^{15}$ 1-MeV-n$_textrm{eq}$/cm$^2$. The sensors were glued to ATLAS FE-I4 pixel readout chips and measured at the CERN SPS H8 beamline using the FE-I4 beam telescope. Results for all fluences are very encouraging with all hit efficiencies being better than 97% for bias voltages of $85,$V. The sample irradiated to a fluence of $1cdot 10^{15}$ n$_textrm{eq}$/cm$^2$ - a relevant value for a large volume of the upgraded tracker - exhibited 99.7% average hit efficiency. The results give strong evidence for the radiation tolerance of HV-CMOS sensors and their suitability as sensors for the experimental HL-LHC upgrades and future large-area silicon-based tracking detectors in high-radiation environments.
The barrel region of the CMS pixel detector will be equipped with ``n-in-n type silicon sensors. They are processed on DOFZ material, use the moderated p-spray technique and feature a bias grid. The latter leads to a small fraction of the pixel area to be less sensitive to particles. In order to quantify this inefficiency prototype pixel sensors irradiated to particle fluences between $4.7times 10^{13}$ and $2.6times 10^{15} Neq$ have been bump bonded to un-irradiated readout chips and tested using high energy pions at the H2 beam line of the CERN SPS. The readout chip allows a non zero suppressed analogue readout and is therefore well suited to measure the charge collection properties of the sensors. In this paper we discuss the fluence dependence of the collected signal and the particle detection efficiency. Further the position dependence of the efficiency is investigated.
SOI (Silicon-On-Insulator) pixel sensor is promising technology for developing the high position resolution detector by integrating the small pixels and circuits in the monolithic way. The event driven (trigger mode) SOI based pixel sensor has also been developed for the application of X-ray astronomy with the purpose of reducing the noise using anti-coincidence event. This trigger mode SOI pixel sensor working with in the rate of kilo Hz is also a promising scatter detector for advanced Compton imaging to track the Compton recoiled electrons.