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Evidence of Water-related Discrete Trap State Formation in Pentacene Single Crystal Field-Effect Transistors

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 Added by Claudia Goldmann
 Publication date 2005
  fields Physics
and research's language is English




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We report on the generation of a discrete trap state during negative gate bias stress in pentacene single crystal flip-crystal field-effect transistors with a SiO2 gate dielectric. Trap densities of up to 2*10^12 cm^-2 were created in the experiments. Trap formation and trap relaxation are distinctly different above and below ~280 K. In devices in which a self-assembled monolayer on top of the SiO2 provides a hydrophobic insulator surface we do not observe trap formation. These results indicate the microscopic cause of the trap state to be water adsorbed on the SiO2 surface.



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Pentacenequinone (PnQ) impurities have been introduced into a pentacene source material at number densities from 0.001 to 0.474 to quantify the relative effects of impurity content and grain boundary structure on transport in pentacene thin-film transistors. Atomic force microscopy (AFM) and electrical measurements of top-contact pentacene thin-film transistors have been employed to directly correlate initial structure and final film structures, with the device mobility as a function of added impurity content. The results reveal a factor four decrease in mobility without significant changes in film morphology for source PnQ number fractions below ~0.008. For these low concentrations, the impurity thus directly influences transport, either as homogeneously distributed defects or by concentration at the otherwise-unchanged grain boundaries. For larger impurity concentrations, the continuing strong decrease in mobility is correlated with decreasing grain size, indicating an impurity-induced increase in the nucleation of grains during early stages of film growth.
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