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Designs for a two-dimensional Si quantum dot array with spin qubit addressability

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 Added by Masahiro Tadokoro
 Publication date 2021
  fields Physics
and research's language is English




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Electron spins in Si are an attractive platform for quantum computation, backed with their scalability and fast, high-fidelity quantum logic gates. Despite the importance of two-dimensional integration with efficient connectivity between qubits for medium- to large-scale quantum computation, however, a practical device design that guarantees qubit addressability is yet to be seen. Here, we propose a practical 3 x 3 quantum dot device design and a larger-scale design as a longer-term target. The design goal is to realize qubit connectivity to the four nearest neighbors while ensuring addressability. We show that a 3 x 3 quantum dot array can execute four-qubit Grovers algorithm more efficiently than the one-dimensional counterpart. To scale up the two-dimensional array beyond 3 x 3, we propose a novel structure with ferromagnetic gate electrodes. Our results showcase the possibility of medium-sized quantum processors in Si with fast quantum logic gates and long coherence times.



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We report the first complete characterization of single-qubit and two-qubit gate fidelities in silicon-based spin qubits, including cross-talk and error correlations between the two qubits. To do so, we use a combination of standard randomized benchmarking and a recently introduced method called character randomized benchmarking, which allows for more reliable estimates of the two-qubit fidelity in this system. Interestingly, with character randomized benchmarking, the two-qubit CPhase gate fidelity can be obtained by studying the additional decay induced by interleaving the CPhase gate in a reference sequence of single-qubit gates only. This work sets the stage for further improvements in all the relevant gate fidelities in silicon spin qubits beyond the error threshold for fault-tolerant quantum computation.
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