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Register a new userAtomically sharp interface enabled ultrahigh-speed, nonvolatile memory devices
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Development of memory devices with ultimate performance has played a key role in innovation of modern electronics. As a mainstream technology nonvolatile memory devices have manifested high capacity and mechanical reliability, however current major bottlenecks include low extinction ratio and slow operational speed. Although substantial effort has been employed to improve their performance, a typical hundreds of micro- or even milli- second write time remains a few orders of magnitude longer than their volatile counterparts. We have demonstrated nonvolatile, floating-gate memory devices based on van der Waals heterostructures with atomically sharp interfaces between different functional elements, and achieved ultrahigh-speed programming/erasing operations verging on an ultimate theoretical limit of nanoseconds with extinction ratio up to 10^10. This extraordinary performance has allowed new device capabilities such as multi-bit storage, thus opening up unforeseen applications in the realm of modern nanoelectronics and offering future fabrication guidelines for device scale-up.
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We describe an all-optical lithography process that can be used to make electrical contact to atomic-precision donor devices made in silicon using scanning tunneling microscopy (STM). This is accomplished by implementing a cleaning procedure in the STM that allows the integration of metal alignment marks and ion-implanted contacts at the wafer level. Low-temperature transport measurements of a patterned device establish the viability of the process.
Recent advances in guiding and localizing light at the nanoscale exposed the enormous potential of ultra-scaled plasmonic devices. In this context, the decay of surface plasmons to hot carriers triggers a variety of applications in boosting the efficiency of energy-harvesting, photo-catalysis and photo-detection. However, a detailed understanding of plasmonic hot carrier generation and particularly the transfer at metal-semiconductor interfaces is still elusive. In this paper, we introduce a monolithic metal-semiconductor (Al-Ge) heterostructure device, providing a platform to examine surface plasmon decay and hot electron transfer at an atomically sharp Schottky nanojunction. The gated metal-semiconductor heterojunction device features electrostatic control of the Schottky barrier height at the Al-Ge interface, enabling hot electron filtering. The ability of momentum matching and to control the energy distribution of plasmon-driven hot electron injection is demonstrated by controlling the interband electron transfer in Ge leading to negative differential resistance.
The operation of resistive and phase-change memory (RRAM and PCM) is controlled by highly localized self-heating effects, yet detailed studies of their temperature are rare due to challenges of nanoscale thermometry. Here we show that the combination of Raman thermometry and scanning thermal microscopy (SThM) can enable such measurements with high spatial resolution. We report temperature-dependent Raman spectra of HfO$_2$, TiO$_2$ and Ge$_2$Sb$_2$Te$_5$ (GST) films, and demonstrate direct measurements of temperature profiles in lateral PCM devices. Our measurements reveal that electrical and thermal interfaces dominate the operation of such devices, uncovering a thermal boundary resistance of 30 m$^2$K$^{-1}$GW$^{-1}$ at GST-SiO$_2$ interfaces and an effective thermopower 350 $mu$V/K at GST-Pt interfaces. We also discuss possible pathways to apply Raman thermometry and SThM techniques to nanoscale and vertical resistive memory devices.
Contact hysteresis between sliding interfaces is a widely observed phenomenon from macro- to nano- scale sliding interfaces. Most of such studies are done using an atomic force microscope (AFM) where the sliding speed is a few {mu}m/s. Here, we present a unique study on stiction between the head-disk interface of commercially available hard disk drives, wherein vertical clearance between the head and the disk is of the same order as in various AFM based fundamental studies, but with a sliding speed that is nearly six orders of magnitude higher. We demonstrate that although the electrostatic force (DC or AC voltage) is an attractive force, the AC voltage induced out-of-plane oscillation of the head with respect to disk is able to suppress completely the contact hysteresis.
Analogous to conventional charge-based electronics, valleytronics aims at encoding data via the valley degree of freedom, enabling new routes for information processing. Long-lived interlayer excitons (IXs) in van der Waals heterostructures (HSs) stacked by transition metal dichalcogenides (TMDs) carry valley-polarized information and thus could find promising applications in valleytronic devices. Although great progress of studies on valleytronic devices has been achieved, nonvolatile valleytronic memory, an indispensable device in valleytronics, is still lacking up to date. Here, we demonstrate an IX-based nonvolatile valleytronic memory in a WS2/WSe2 HS. In this device, the emission characteristics of IXs exhibit a large excitonic/valleytronic hysteresis upon cyclic-voltage sweeping, which is ascribed to the chemical-doping of O2/H2O redox couple trapped between the TMDs and substrate. Taking advantage of the large hysteresis, the first nonvolatile valleytronic memory has been successfully made, which shows a good performance with retention time exceeding 60 minutes. These findings open up an avenue for nonvolatile valleytronic memory and could stimulate more investigations on valleytronic devices.
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