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Register a new userAndreev interference in the surface accumulation layer of half-shell InAsSb/Al hybrid nanowires
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Understanding the spatial distribution of charge carriers in III-V nanowires proximity coupled to superconductors is important for the design and interpretation of experiments based on hybrid quantum devices. In this letter, the gate-dependent surface accumulation layer of InAsSb/Al nanowires was studied by means of Andreev interference in a parallel magnetic field. Both uniform hybrid nanowires and devices featuring a short Josephson junction fabricated by shadow lithography, exhibited periodic modulation of the switching current. The period corresponds to a flux quantum through the nanowire diameter and is consistent with Andreev bound states occupying a cylindrical surface accumulation layer. The spatial distribution was tunable by a gate potential as expected from electrostatic models.
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We study the electronic properties of InAs/EuS/Al heterostructures as explored in a recent experiment [S. Vaitiekenas emph{et al.}, Nat. Phys. (2020)], combining both spectroscopic results and microscopic device simulations. In particular, we use angle-resolved photoemission spectroscopy to investigate the band bending at the InAs/EuS interface. The resulting band offset value serves as an essential input to subsequent microscopic device simulations, allowing us to map the electronic wave function distribution. We conclude that the magnetic proximity effects at the Al/EuS as well as the InAs/EuS interfaces are both essential to achieve topological superconductivity at zero applied magnetic field. Mapping the topological phase diagram as a function of gate voltages and proximity-induced exchange couplings, we show that the ferromagnetic hybrid nanowire with overlapping Al and EuS layers can become a topological superconductor within realistic parameter regimes, and that the topological phase can be optimized by external gating. Our work highlights the need for a combined experimental and theoretical effort for faithful device simulation.
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