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Register a new userUltra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications
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The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer.
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To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.
Three-dimensional (3D)-stacking technology, which enables the integration of DRAM and logic dies, offers high bandwidth and low energy consumption. This technology also empowers new memory designs for executing tasks not traditionally associated with memories. A practical 3D-stacked memory is Hybrid Memory Cube (HMC), which provides significant access bandwidth and low power consumption in a small area. Although several studies have taken advantage of the novel architecture of HMC, its characteristics in terms of latency and bandwidth or their correlation with temperature and power consumption have not been fully explored. This paper is the first, to the best of our knowledge, to characterize the thermal behavior of HMC in a real environment using the AC-510 accelerator and to identify temperature as a new limitation for this state-of-the-art design space. Moreover, besides bandwidth studies, we deconstruct factors that contribute to latency and reveal their sources for high- and low-load accesses. The results of this paper demonstrates essential behaviors and performance bottlenecks for future explorations of packet-switched and 3D-stacked memories.
A procedure to achieve the density-controlled growth of gold-catalyzed InP nanowires (NWs) on (111) silicon substrates using the vapor-liquid-solid method by molecular beam epitaxy is reported. We develop an effective and mask-free method based on controlling the number and the size of the Au-In catalyst droplets in addition to the conditions for the NW nucleation. We show that the NW density can be tuned with values in the range of 18 {mu}m-2 to < 0.1 {mu}m-2 by the suitable choice of the In/Au catalyst beam equivalent pressure (BEP) ratio, by the phosphorous BEP and the growth temperature. The same degree of control is transferred to InAs/InP quantum dot-nanowires, taking advantage of the ultra-low density to study by micro-photoluminescence the optical properties of a single quantum dot-nanowires emitting in the telecom band monolithically grown on silicon. Optical spectroscopy at cryogenic temperature successfully confirmed the relevance of our method to excite single InAs quantum dots on the as-grown sample, which opens the path for large-scale applications based on single quantum dot-nanowire devices integrated on silicon.
Memories that exploit three-dimensional (3D)-stacking technology, which integrate memory and logic dies in a single stack, are becoming popular. These memories, such as Hybrid Memory Cube (HMC), utilize a network-on-chip (NoC) design for connecting their internal structural organizations. This novel usage of NoC, in addition to aiding processing-in-memory capabilities, enables numerous benefits such as high bandwidth and memory-level parallelism. However, the implications of NoCs on the characteristics of 3D-stacked memories in terms of memory access latency and bandwidth have not been fully explored. This paper addresses this knowledge gap by (i) characterizing an HMC prototype on the AC-510 accelerator board and revealing its access latency behaviors, and (ii) by investigating the implications of such behaviors on system and software designs.
Since the experimental discovery of magnetic skyrmions achieved one decade ago, there have been significant efforts to bring the virtual particles into all-electrical fully functional devices, inspired by their fascinating physical and topological properties suitable for future low-power electronics. Here, we experimentally demonstrate such a device: electrically-operating skyrmion-based artificial synaptic device designed for neuromorphic computing. We present that controlled current-induced creation, motion, detection and deletion of skyrmions in ferrimagnetic multilayers can be harnessed in a single device at room temperature to imitate the behaviors of biological synapses. Using simulations, we demonstrate that such skyrmion-based synapses could be used to perform neuromorphic pattern-recognition computing using handwritten recognition data set, reaching to the accuracy of ~89 percents, comparable to the software-based training accuracy of ~94 percents. Chip-level simulation then highlights the potential of skyrmion synapse compared to existing technologies. Our findings experimentally illustrate the basic concepts of skyrmion-based fully functional electronic devices while providing a new building block in the emerging field of spintronics-based bio-inspired computing.
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