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Register a new userDesign of a Time-to-Digital Converter ASIC and a mini-DAQ system for the Phase-2 Upgrade of the ATLAS Monitored Drift Tube detector
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We present the second prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for High-Luminosity LHC operations. Compared to the first prototype, triple modular redundancy has been implemented for the configuration and flow control logic. The total power consumption is increased by less than 10 mW while achieving the same time resolution and channel uniformity. A mini-DAQ system has been built to verify the front-end electronics chain with the new prototype together with other ASICs and boards in triggered mode. Cosmic ray tests with a small-diameter MDT chamber indicate that the configuration and data transmission of the readout electronics perform well. It is expected that this prototype design will be used in the final production.
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A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detectors PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0:3mV ~ 3V; 0:2 ~ 2500 pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.
We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of High-Luminosity LHC upgrade. One of the challenges of the ETROC design is that the TDC is required to consume less than 200 W for each pixel at the nominal hit occupancy of 1%. To meet the low-power requirement, we use a single delay line for both the Time of Arrival (TOA) and the Time over Threshold (TOT) measurements without delay control. A double-strobe self-calibration scheme is used to compensate for process variation, temperature, and power supply voltage. The TDC is fabricated in a 65 nm CMOS technology. The overall performances of the TDC have been evaluated. The TOA has a bin size of 17.8 ps within its effective dynamic range of 11.6 ns. The effective measurement precision of the TOA is 5.6 ps and 9.9 ps with and without the nonlinearity correction, respectively. The TDC block consumes 97 W at the hit occupancy of 1%. Over a temperature range from 23 C to 78 C and a power supply voltage range from 1.05 V to 1.35 V (the nominal value of 1.20 V), the self-calibrated bin size of the TOA varies within 0.4%. The measured TDC performances meet the requirements except that more tests will be performed in the future to verify that the TDC complies with the radiation-tolerance specifications.
The influence of fast neutrons on the occupancy and the single tube resolution of ATLAS muon drift detectors was investigated by exposing a chamber built out of 3 layers of 3 short standard drift tubes to neutron flux-densities of up to 16 kHz/cm2 at a neutron energy of E=11 MeV. Pulse shape capable NE213 scintillaton detectors and a calibrated BF3 neutron detector provided monitoring of the neutron flux-density and energy. The sensitivity of the drift chamber to the neutrons was measured to be 4*10-4 by comparing data sets with and without neutron background. For the investigation of tracks of cosmic muons two silicon-strip detectors above and underneath the chamber allow to compare measured drift-radii with reference tracks. Alternatively, the single tube resolution was determined using the triple-sum method. The comparison between data with and without neutron irradiation shows only a marginal effect on the resolution and little influence on the muon track reconstruction.
We present the characterization and quality control test of a gigabit cable receiver ASIC prototype, GBCR2, for the ATLAS Inner Tracker pixel detector upgrade. GBCR2 equalizes and retimes the uplink electrical signals from RD53B through a 6 m Twinax AWG34 cable to lpGBT. GBCR2 also pre-emphasizes downlink command signals through the same electrical connection from lpGBT to RD53B. GBCR2 has seven uplink channels each at 1.28 Gbps and two downlink channels each at 160 Mbps. The prototype is fabricated in a 65 nm CMOS process. The characterization of GBCR2 has been demonstrated that the total jitter of the output signal is 129.1 ps (peak-peak) in the non-retiming mode or 79.3 ps (peak-peak) in the retiming mode for the uplink channel and meets the requirements of lpGBT. The total power consumption of all uplink channels is 87.0 mW in the non-retiming mode and 101.4 mW in the retiming mode, below the specification of 174 mW. The two downlink channels consume less than 53 mW. A quality control test procedure is proposed and 169 prototype chips are tested. The yield is about 97.0%.
In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a Time to Digital Converter (TDC) with 625 ps resolution (LSB) along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. We will describe briefly the architecture of the TDC and of the Data AcQuisition (DAQ) system. Some more details will be provided about the zero-suppression algorithm used to reduce the data throughput.
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