Subscribe to the gold package and get unlimited access to Shamra Academy
Register a new userCooling and Timing tests of the ATLAS Fast Tracker VME boards
59
0
0.0
(
0
)
Added by
Simone Sottocornola
Publication date
2020
fields
Physics
and research's language is
English
Ask ChatGPT about the research
No Arabic abstract
The Fast Tracker (FTK) is an ATLAS trigger upgrade built for full event, low-latency, high-rate tracking. The FTK core, made of 9U VME boards, performs the most demanding computational task. The Associative Memory Board Serial Link Processor (AMB) and the Auxiliary card (AUX), plugged on the front and back sides of the same VME slot, constitute the Processing Unit (PU), which finds tracks using hits from 8 layers of the inner detector. The PU works in pipeline with the Second Stage Board (SSB), which finds 12-layer tracks by adding extra hits to the identified tracks. In the designed configuration, 16 PUs and 4 SSBs are installed in a VME crate. The high power-consumption of the AMB, AUX and SSB (respectively of about 250 W, 70 W and 160 W per board) required the development of a custom cooling system. Even though the expected power consumption for each VME crate of the FTK system is high compared to a common VME setup, the 8 FTK core crates will use $approx$ 60 kW, which is just a fraction of the power and the space needed for a CPU farm performing the same task. We report on the integration of 32 PUs and 8 SSBs inside the FTK system, on the infrastructures needed to run and cool them, and on the tests performed to verify the system processing rate and the temperature stability at a safe value.
rate research
Read More
The SemiConductor Tracker (SCT) together with the Pixel detector and the Transition Radiation Tracker (TRT) form the central tracking system of the ATLAS experiment at the LHC. It consists of single-sided microstrip silicon sensors, which are read out via binary ASICs based on the DMILL technology, and the data are transmitted via radiation-hard optical fibres. After an overview of the SCT detector layout and readout system, the final-stage assembly of large-scale structures and the integration with the TRT is presented. The focus is on the electrical performance of the overall SCT detector system through the different integration stages, including the detector control and data acquisition system.
ATLAS is making extensive efforts towards preparing a detector upgrade for the high luminosity operations of the LHC (HL-LHC), which will commence operation in about 10 years. The current ATLAS Inner Detector will be replaced by an all-silicon tracker (comprising an inner Pixel tracker and outer Strip tracker). The software currently used for the new silicon tracker is broadly inherited from that used for the LHC Run-1 and Run-2, but many new developments have been made to better fulfill the future detector and operation requirements. One aspect in particular which will be highlighted is the simulation software for the Strip tracker. The available geometry description software (including the detailed description for all the sensitive elements, the services, etc.) did not allow for accurate modelling of the planned detector design. A range of sensors/layouts for the Strip tracker are being considered and must be studied in detailed simulations in order to assess the performance and ascertain that requirements are met. For this, highly flexibility geometry building is required from the simulation software. A new Xml-based detector description framework has been developed to meet the aforementioned challenges. We will present the design of the framework and its validation results.
For the Phase-II Upgrade of the ATLAS Detector, its Inner Detector, consisting of silicon pixel, silicon strip and transition radiation sub-detectors, will be replaced with an all new 100 % silicon tracker, composed of a pixel tracker at inner radii and a strip tracker at outer radii. The future ATLAS strip tracker will include 11,000 silicon sensor modules in the central region (barrel) and 7,000 modules in the forward region (end-caps), which are foreseen to be constructed over a period of 3.5 years. The construction of each module consists of a series of assembly and quality control steps, which were engineered to be identical for all production sites. In order to develop the tooling and procedures for assembly and testing of these modules, two series of major prototyping programs were conducted: an early program using readout chips designed using a 250 nm fabrication process (ABCN-25) and a subsequent program using a follow-up chip set made using 130 nm processing (ABC130 and HCC130 chips). This second generation of readout chips was used for an extensive prototyping program that produced around 100 barrel-type modules and contributed significantly to the development of the final module layout. This paper gives an overview of the components used in ABC130 barrel modules, their assembly procedure and findings resulting from their tests.
In next ten years, the Large Hadron Collider will be upgraded to the High Luminosity LHC (HL-LHC), resulting in ten time more integrated luminosity. To withstand the much harsher radiation and occupancy conditions of the HL-LHC, the inner tracker of the ATLAS detector must be redesigned and rebuilt completely. The design of the ATLAS Upgrade inner tracker (ITk) has already been defined. It consists of several layers of silicon particle detectors. The innermost layers will be composed of silicon pixel sensors, and the outer layers will consist of silicon microstrip sensors. This paper will focus on the latest research and development activities performed by ITk strips community with respect to the assembly and test of the strip modules and the stave and petal structures.
Results of beam tests with planar silicon pixel sensors aimed towards the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include spatial resolution, charge collection performance and charge sharing between neighbouring cells as a function of track incidence angle for different bulk materials. Measurements of n-in-n pixel sensors are presented as a function of fluence for different irradiations. Furthermore p-type silicon sensors from several vendors with slightly differing layouts were tested. All tested sensors were connected by bump-bonding to the ATLAS Pixel read-out chip. We show that both n-type and p-type tested planar sensors are able to collect significant charge even after integrated fluences expected at HL-LHC.
Log in to be able to interact and post comments
comments
Fetching comments
Sign in to be able to follow your search criteria
