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Two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDs) are good candidates for high-performance flexible electronics. However, most demonstrations of such flexible field-effect transistors (FETs) to date have been on the micron scale, not benefitting from the short-channel advantages of 2D-TMDs. Here, we demonstrate flexible monolayer MoS2 FETs with the shortest channels reported to date (down to 50 nm) and remarkably high on-current (up to 470 uA/um at 1 V drain-to-source voltage) which is comparable to flexible graphene or crystalline silicon FETs. This is achieved using a new transfer method wherein contacts are initially patterned on the rigid TMD growth substrate with nanoscale lithography, then coated with a polyimide (PI) film which becomes the flexible substrate after release, with the contacts and TMD. We also apply this transfer process to other TMDs, reporting the first flexible FETs with MoSe2 and record on-current for flexible WSe2 FETs. These achievements push 2D semiconductors closer to a technology for low-power and high-performance flexible electronics.
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Over the past several years, the inherent scaling limitations of electron devices have fueled the exploration of high carrier mobility semiconductors as a Si replacement to further enhance the device performance. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied, combining the high mobility of III-V semiconductors and the well-established, low cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored. Besides complexity, high defect densities and junction leakage currents present limitations in the approach. Motivated by this challenge, here we utilize an epitaxial transfer method for the integration of ultrathin layers of single-crystalline InAs on Si/SiO2 substrates. As a parallel to silicon-on-insulator (SOI) technology14,we use the abbreviation XOI to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsOx layer (~1 nm thick). The fabricated FETs exhibit an impressive peak transconductance of ~1.6 mS/{mu}m at VDS=0.5V with ON/OFF current ratio of greater than 10,000 and a subthreshold swing of 107-150 mV/decade for a channel length of ~0.5 {mu}m.
Starting from graphene, 2D layered materials family has been recently set up more than 100 different materials with variety of different class of materials such as semiconductors, metals, semimetals, superconductors. Among these materials, 2D semiconductors have found especial importance in the state of the art device applications compared to that of the current conventional devices such as (which material based for example Si based) field effect transistors (FETs) and photodetectors during the last two decades. This high potential in solid state devices is mostly revealed by the transition metal dichalcogenides (TMDCs) semiconductor materials such as MoS2 , WS2 , MoSe2 and WSe2 . Therefore, many different methods and approaches have been developed to grow or obtain so far in order to make use them in solid state devices, which is a great challenge in large area applications. Although there are intensively studied methods such as chemical vapor deposition (CVD), mechanical exfoliation, atomic layer deposition, it is sputtering getting attention day by day due to the simplicity of the growth method together with its reliability, large area growth possibility and repeatability. In this review article, we provide benefits and disadvantages of all the growth methods when growing TMDC materials, then focusing on the sputtering TMDC growth strategies performed. In addition, TMDCs for the FETs and photodetector devices grown by RFMS have been surveyed.
We report the radio-frequency performance of carbon nanotube array transistors that have been realized through the aligned assembly of highly separated, semiconducting carbon nanotubes on a fully scalable device platform. At a gate length of 100 nm, we observe output current saturation and obtain as-measured, extrinsic current gain and power gain cut-off frequencies, respectively, of 7 GHz and 15 GHz. While the extrinsic current gain is comparable to the state-of-the-art the extrinsic power gain is improved. The de-embedded, intrinsic current gain and power gain cut-off frequencies of 153 GHz and 30 GHz are the highest values experimentally achieved to date. We analyze the consistency of DC and AC performance parameters and discuss the requirements for future applications of carbon nanotube array transistors in high-frequency electronics.
High contact resistance is one of the primary concerns for electronic device applications of two-dimensional (2D) layered semiconductors. Here, we explore the enhanced carrier transport through metal-semiconductor interfaces in WS2 field effect transistors (FETs) by introducing a typical transition metal, Cu, with two different doping strategies: (i) a generalized Cu doping by using randomly distributed Cu atoms along the channel and (ii) a localized Cu doping by adapting an ultrathin Cu layer at the metal-semiconductor interface. Compared to the pristine WS2 FETs, both the generalized Cu atomic dopant and localized Cu contact decoration can provide a Schottky-to-Ohmic contact transition owing to the reduced contact resistances by 1 - 3 orders of magnitude, and consequently elevate electron mobilities by 5 - 7 times higher. Our work demonstrates that the introduction of transition metal can be an efficient and reliable technique to enhance the carrier transport and device performance in 2D TMD FETs.
Transition-metal dichalcogenides (TMDCs) are important class of two-dimensional (2D) layered materials for electronic and optoelectronic applications, due to their ultimate body thickness, sizable and tunable bandgap, and decent theoretical room-temperature mobility of hundreds to thousands cm2/Vs. So far, however, all TMDCs show much lower mobility experimentally because of the collective effects by foreign impurities, which has become one of the most important limitations for their device applications. Here, taking MoS2 as an example, we review the key factors that bring down the mobility in TMDC transistors, including phonons, charged impurities, defects, and charge traps. We introduce a theoretical model that quantitatively captures the scaling of mobility with temperature, carrier density and thickness. By fitting the available mobility data from literature over the past few years, we are able to obtain the density of impurities and traps for a wide range of transistor structures. We show that interface engineering such as oxide surface passivation, high-k dielectrics and BN encapsulation could effectively reduce the impurities, leading to improved device performances. For few-layer TMDCs, we analytically model the lopsided carrier distribution to elucidate the experimental increase of mobility with the number of layers. From our analysis, it is clear that the charge transport in TMDC samples is a very complex problem that must be handled carefully. We hope that this Review can provide new insights and serve as a starting point for further improving the performance of TMDC transistors.
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