Subscribe to the gold package and get unlimited access to Shamra Academy
Register a new userGate-tunable non-volatile photomemory effect in MoS$_2$ transistors
163
0
0.0
(
0
)
Ask ChatGPT about the research
No Arabic abstract
Non-volatile memory devices have been limited to flash architectures that are complex devices. Here, we present a unique photomemory effect in MoS$_2$ transistors. The photomemory is based on a photodoping effect - a controlled way of manipulating the density of free charges in monolayer MoS$_2$ using a combination of laser exposure and gate voltage application. The photodoping promotes changes on the conductance of MoS$_2$ leading to photomemory states with high memory on/off ratio. Such memory states are non-volatile with an expectation of retaining up to 50 % of the information for tens of years. Furthermore, we show that the photodoping is gate-tunable, enabling control of the recorded memory states. Finally, we propose a model to explain the photodoping, and we provide experimental evidence supporting such a phenomenon. In summary, our work includes the MoS$_2$ phototransistors in the non-volatile memory devices and expands the possibilities of memory application beyond conventional memory architectures.
rate research
Read More
Two-dimensional (2D) transition metal dichalcogenides (TMDs) such as molybdenum disulfide (MoS2) have been intensively investigated because of their exclusive physical properties for advanced electronics and optoelectronics. In the present work, we study the MoS2 transistor based on a novel tri-gate device architecture, with dual-gate (Dual-G) in the channel and the buried side-gate (Side-G) for the source/drain regions. All gates can be independently controlled without interference. For a MoS2 sheet with a thickness of 3.6 nm, the Schottky barrier (SB) and non-overlapped channel region can be effectively tuned by electrostatically doping the source/drain regions with Side-G. Thus, the extrinsic resistance can be effectively lowered, and a boost of the ON-state current can be achieved. Meanwhile, the channel control remains efficient under the Dual-G mode, with an ON-OFF current ratio of 3E7 and subthreshold swing of 83 mV/decade. The corresponding band diagram is also discussed to illustrate the device operation mechanism. This novel device structure opens up a new way toward fabrication of high-performance devices based on 2D-TMDs.
Monolayer molybdenum disulfide (MoS$_2$) nanosheets, obtained via chemical vapor deposition onto SiO$_2$/Si substrates, are exploited to fabricate field-effect transistors with n-type conduction, high on/off ratio, steep subthreshold slope and good mobility. The transistor channel conductance increases with the reducing air pressure due to oxygen and water desorption. Local field emission measurements from the edges of the MoS$_2$ nanosheets are performed in high vacuum using a tip-shaped anode. It is demonstrated that the voltage applied to the Si substrate back-gate modulates the field emission current. Such a finding, that we attribute to gate-bias lowering of the MoS$_2$ electron affinity, enables a new field-effect transistor based on field emission.
Palladium diselenide (PdSe2) is a recently isolated layered material that has attracted a lot of interest for the pentagonal structure, the air stability and the electrical properties largely tunable by the number of layers. In this work, PdSe2 is used in the form of multilayer as the channel of back-gate field-effect transistors, which are studied under repeated electron irradiations. Source-drain Pd leads enable contacts with resistance below 350 kOhm um. The transistors exhibit a prevailing n-type conduction in high vacuum, which reversibly turns into ambipolar electric transport at atmospheric pressure. Irradiation by 10 keV electrons suppresses the channel conductance and promptly transforms the device from n-type to p-type. An electron fluence as low as 160 e-/nm2 dramatically change the transistor behavior demonstrating a high sensitivity of PdSe2 to electron irradiation. The sensitivity is lost after few exposures, that is a saturation condition is reached for fluence higher than 4000 e-/nm2. The damage induced by high electron fluence is irreversible as the device persist in the radiation-modified state for several hours, if kept in vacuum and at room temperature. With the support of numerical simulation, we explain such a behavior by electron-induced Se atom vacancy formation and charge trapping in slow trap states at the Si/SiO_2 interface.
We report the development of nanowire field-effect transistors featuring an ultra-thin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally-coated nanowires, which we used to produce functional $Omega$-gate and gate-all-around structures. These give sub-threshold swings as low as 140 mV/dec and on/off ratios exceeding $10^3$ at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically-treated nanowire surfaces; a feature generally not possible with oxides produced by atomic layer deposition due to the surface `self-cleaning effect. Our results highlight the potential for parylene as an alternative ultra-thin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylenes well-established biocompatible properties.
We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique. Top gates were then defined aligned to the bottom gates to form gate-all-around structures. This approach overcomes significant limitations in minimal obtainable gate length and gate-length control in previous horizontal wrap-gated nanowire transistors that arise because the gate is defined by wet etching. In the method presented here gate-length control is limited by the resolution of the electron-beam-lithography process. We demonstrate the versatility of our approach by fabricating a device with an independent bottom gate, top gate, and gate-all-around structure as well as a device with three independent gate-all-around structures with 300 nm, 200 nm, and 150 nm gate length. Our method enables us to achieve sub-threshold swings as low as 38 mV/dec at 77 K for a 150 nm gate length.
Log in to be able to interact and post comments
comments
Fetching comments
Sign in to be able to follow your search criteria
