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Register a new userTop Dielectric Induced Ambipolarity in an n-channel dual-gated Organic Field Effect Transistor
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Added by
Francesco Calavalle
Publication date
2020
fields
Physics
and research's language is
English
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The realization of both p-type and n-type operations in a single organic field effect transistor (OFET) is critical for simplifying the design of complex organic circuits. Typically, only p-type or n-type operation is realized in an OFET, while the respective counterpart is either suppressed by charge trapping or limited by the injection barrier with the electrodes. Here we show that only the presence of a top dielectric turns an n-type polymer semiconductor (N2200, Polyera ActiveInk) into an ambipolar one, as detected from both bottom and top gated OFET operation. The effect is independent of the channel thickness and the top dielectric combinations. Variable temperature transfer characteristics show that both the electrons and holes can be equally transported through the bulk of the polymer semiconductor.
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Polymer field-effect transistors with 2D graphene electrodes are devices that merge the best of two worlds: on the one hand, the low-cost and processability of organic materials and, on the other hand, the chemical robustness, extreme thinness and flexibility of graphene. Here, we demonstrate the tuning of the ambipolar nature of the semiconductor polymer N2200 from Polyera ActiveInk by incorporating graphene electrodes in a transistor geometry. Our devices show a balanced ambipolar behavior with high current ON-OFF ratio and charge carrier mobilities. These effects are caused by both the effective energy barrier modulation and by the weak electric field screening effect at the graphene-polymer interface. Our results provide a strategy to integrate 2D graphene electrodes in ambipolar transistors in order to improve and modulate their characteristics, paving the way for the design of novel organic electronic devices.
In this work we test graphene electrodes in nano-metric channel n-type Organic Field EffectTransistors (OFETs) based on thermally evaporated thin films of perylene-3,4,9,10-tetracarboxylic acid diimide derivative (PDIF-CN2). By a thorough comparison with short channel transistors made with reference gold electrodes, we found that the output characteristics of the graphene-based devices respond linearly to the applied biases, in contrast with the supra-linear trend of gold-based transistors. Moreover, short channel effects are considerably suppressed in graphene electrodes devices. More specifically, current on/off ratios independent of the channel length (L) and enhanced response for high longitudinal biases are demonstrated for L down to ~140 nm. These results are rationalized taking into account the morphological and electronic characteristics of graphene, showing that the use of graphene electrodes may help to overcome the problem of Space Charge Limited Current (SCLC) in short channel OFETs.
In 1963, Moll and Tarui suggested that the field-effect conductance of a semiconductor could be controlled by the remanent polarization of a ferroelectric (FE) material to create a ferroelectric field-effect transistor (FE-FET). However, subsequent efforts to produce a practical, compact FE-FET have been plagued by low retention and incompatibility with Complementary Metal Oxide Semiconductor (CMOS) process integration. These difficulties led to the development of trapped-charge based memory devices (also called floating gate or flash memory), and these are now the mainstream non-volatile memory (NVM) technology. Over the past two decades, advances in oxide FE materials have rejuvenated the field of ferroelectrics and made FE random access memories (FE-RAM) a commercial reality. Despite these advances, commercial FE-RAM based on lead zirconium titanate (PZT) has stalled at the 130 nm due to process challenges.The recent discovery of scandium doped aluminum nitride (AlScN) as a CMOS compatible ferroelectric presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approx. 350 C). This temperature is compatible with CMOS back end of line processes. Here, we present a FE-FET device composed of an AlScN FE dielectric layer integrated with a channel layer of a van der Waals two-dimensional (2D) semiconductor, MoS2. Our devices show an ON/OFF ratio ~ 10^6, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable, two-state memory retention for up to 10^4 seconds. Our simulations and experimental results suggest that the combination of AlScN and 2D semiconductors is nearly ideal for low power FE-FET memory. These results demonstrate a new approach in embedded memory and in-memory computing, and could even lead to effective neuromorphic computing architectures.
Ferroelectric field-effect transistors employ a ferroelectric material as a gate insulator, the polarization state of which can be detected using the channel conductance of the device. As a result, the devices are of potential to use in non-volatile memory technology, but suffer from short retention times, which limits their wider application. Here we report a ferroelectric semiconductor field-effect transistor in which a two-dimensional ferroelectric semiconductor, indium selenide ({alpha}-In2Se3), is used as the channel material in the device. {alpha}-In2Se3 was chosen due to its appropriate bandgap, room temperature ferroelectricity, ability to maintain ferroelectricity down to a few atomic layers, and potential for large-area growth. A passivation method based on the atomic-layer deposition of aluminum oxide (Al2O3) was developed to protect and enhance the performance of the transistors. With 15-nm-thick hafnium oxide (HfO2) as a scaled gate dielectric, the resulting devices offer high performance with a large memory window, a high on/off ratio of over 108, a maximum on-current of 862 {mu}A {mu}m-1, and a low supply voltage.
We report the development of nanowire field-effect transistors featuring an ultra-thin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally-coated nanowires, which we used to produce functional $Omega$-gate and gate-all-around structures. These give sub-threshold swings as low as 140 mV/dec and on/off ratios exceeding $10^3$ at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically-treated nanowire surfaces; a feature generally not possible with oxides produced by atomic layer deposition due to the surface `self-cleaning effect. Our results highlight the potential for parylene as an alternative ultra-thin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylenes well-established biocompatible properties.
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