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Register a new userA Ferroelectric Semiconductor Field-Effect Transistor
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Ferroelectric field-effect transistors employ a ferroelectric material as a gate insulator, the polarization state of which can be detected using the channel conductance of the device. As a result, the devices are of potential to use in non-volatile memory technology, but suffer from short retention times, which limits their wider application. Here we report a ferroelectric semiconductor field-effect transistor in which a two-dimensional ferroelectric semiconductor, indium selenide ({alpha}-In2Se3), is used as the channel material in the device. {alpha}-In2Se3 was chosen due to its appropriate bandgap, room temperature ferroelectricity, ability to maintain ferroelectricity down to a few atomic layers, and potential for large-area growth. A passivation method based on the atomic-layer deposition of aluminum oxide (Al2O3) was developed to protect and enhance the performance of the transistors. With 15-nm-thick hafnium oxide (HfO2) as a scaled gate dielectric, the resulting devices offer high performance with a large memory window, a high on/off ratio of over 108, a maximum on-current of 862 {mu}A {mu}m-1, and a low supply voltage.
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In 1963, Moll and Tarui suggested that the field-effect conductance of a semiconductor could be controlled by the remanent polarization of a ferroelectric (FE) material to create a ferroelectric field-effect transistor (FE-FET). However, subsequent efforts to produce a practical, compact FE-FET have been plagued by low retention and incompatibility with Complementary Metal Oxide Semiconductor (CMOS) process integration. These difficulties led to the development of trapped-charge based memory devices (also called floating gate or flash memory), and these are now the mainstream non-volatile memory (NVM) technology. Over the past two decades, advances in oxide FE materials have rejuvenated the field of ferroelectrics and made FE random access memories (FE-RAM) a commercial reality. Despite these advances, commercial FE-RAM based on lead zirconium titanate (PZT) has stalled at the 130 nm due to process challenges.The recent discovery of scandium doped aluminum nitride (AlScN) as a CMOS compatible ferroelectric presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approx. 350 C). This temperature is compatible with CMOS back end of line processes. Here, we present a FE-FET device composed of an AlScN FE dielectric layer integrated with a channel layer of a van der Waals two-dimensional (2D) semiconductor, MoS2. Our devices show an ON/OFF ratio ~ 10^6, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable, two-state memory retention for up to 10^4 seconds. Our simulations and experimental results suggest that the combination of AlScN and 2D semiconductors is nearly ideal for low power FE-FET memory. These results demonstrate a new approach in embedded memory and in-memory computing, and could even lead to effective neuromorphic computing architectures.
The elegant simplicity of the device concept and the urgent need for a new transistor at the twilight of Moores law have inspired many researchers in industry and academia to explore the physics and technology of negative capacitance field effect transistor (NC-FET). Although hundreds of papers have been published, the validity of quasi-static NC and the frequency-reliability limits of NC-FET are still being debated. The concept of NC - if conclusively demonstrated - will have broad impacts on device physics and technology development. Here, the authors provide a critical review of recent progress on NC-FETs research and some starting points for a coherent discussion.
The ferroelectric polarization switching in ferroelectric hafnium zirconium oxide (Hf0.5Zr0.5O2, HZO) in the HZO/Al2O3 ferroelectric/dielectric stack is investigated systematically by capacitance-voltage and polarization-voltage measurements. The thickness of dielectric layer is found to have a determinant impact on the ferroelectric polarization switching of ferroelectric HZO. A suppression of ferroelectricity is observed with thick dielectric layer. In the gate stacks with thin dielectric layers, a full polarization switching of the ferroelectric layer is found possible by the proposed leakage-current-assist mechanism through the ultrathin dielectric layer. Theoretical simulation results agree well with experimental data. This work clarifies some of the critical parts of the long-standing confusions and debating related to negative capacitance field-effect transistors (NC-FETs) concepts and experiments.
Polymer field-effect transistors with 2D graphene electrodes are devices that merge the best of two worlds: on the one hand, the low-cost and processability of organic materials and, on the other hand, the chemical robustness, extreme thinness and flexibility of graphene. Here, we demonstrate the tuning of the ambipolar nature of the semiconductor polymer N2200 from Polyera ActiveInk by incorporating graphene electrodes in a transistor geometry. Our devices show a balanced ambipolar behavior with high current ON-OFF ratio and charge carrier mobilities. These effects are caused by both the effective energy barrier modulation and by the weak electric field screening effect at the graphene-polymer interface. Our results provide a strategy to integrate 2D graphene electrodes in ambipolar transistors in order to improve and modulate their characteristics, paving the way for the design of novel organic electronic devices.
In this work, we demonstrate high performance indium-tin-oxide (ITO) transistors with the channel thickness down to 1 nm and ferroelectric Hf0.5Zr0.5O2 as gate dielectric. On-current of 0.243 A/mm is achieved on sub-micron gate-length ITO transistors with a channel thickness of 1 nm, while it increases to as high as 1.06 A/mm when the channel thickness increases to 2 nm. A raised source/drain structure with a thickness of 10 nm is employed, contributing to a low contact resistance of 0.15 {Omega}mm and a low contact resistivity of 1.1{times}10-7 {Omega}cm2. The ITO transistor with a recessed channel and ferroelectric gating demonstrates several advantages over 2D semiconductor transistors and other thin film transistors, including large-area wafer-size nanometer thin film formation, low contact resistance and contact resistivity, atomic thin channel being immunity to short channel effects, large gate modulation of high carrier density by ferroelectric gating, high-quality gate dielectric and passivation formation, and a large bandgap for the low-power back-end-of-line (BEOL) CMOS application.
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