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Register a new userThe Investigation of Negative Capacitance Vertical Nanowire FETs Based on SPICE Model at Device-Circuit Level
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Weixing Huang
Publication date
2020
fields
Informatics Engineering
and research's language is
English
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In this study, a SPICE model for negative capacitance vertical nanowire field-effect-transistor (NC VNW-FET) based on BSIM-CMG model and Landau-Khalatnikov (LK) equation was presented. Suffering from the limitation of short gate length there is lack of controllable and integrative structures for high performance NC VNW-FETs. A new kind of structure was proposed for NC VNW-FETs at sub-3nm node. Moreover, in order to understand and improve NC VNW-FETs, the S-shaped polarization-voltage curve (S-curve) was divided into four regions and some new design rules were proposed. By using the SPICE model, device-circuit co-optimization was implemented. The co-design of gate work function (WF) and NC was investigated. A ring oscillator was simulated to analyze the circuit energy-delay, and it shown that significant energy reduction, up to 88%, at iso-delay for NC VNW-FETs at low supply voltage can be achieved. This study gives a credible method to analysis the performance of NC based devices and circuits and reveals the potential of NC VNW-FETs in low-power applications.
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The electronic property of NiFe$_2$O$_4$ nanowire device is investigated through nonequilibrium Greens functions (NEGF) in combination with density functional theory (DFT). The electronic transport properties of NiFe$_2$O$_4$ nanowire are studied in terms of density of states, transmission spectrum and $I{-}V$ characteristics. The density of states gets modified with the applied bias voltage across NiFe$_2$O$_4$ nanowire device, the density of charge is observed both in the valence band and in the conduction band on increasing the bias voltage. The transmission spectrum of NiFe$_2$O$_4$ nanowire device gives the insights on the transition of electrons at different energy intervals. The findings of the present work suggest that NiFe$_2$O$_4$ nanowire device can be used as negative differential resistance (NDR) device and its NDR property can be tuned with the bias voltage, which may be used in microwave device, memory devices and in fast switching devices.
A Boltzmann machine whose effective temperature can be dynamically cooled provides a stochastic neural network realization of simulated annealing, which is an important metaheuristic for solving combinatorial or global optimization problems with broad applications in machine intelligence and operations research. However, the hardware realization of the Boltzmann stochastic element with cooling capability has never been achieved within an individual semiconductor device. Here we demonstrate a new memristive device concept based on two-dimensional material heterostructures that enables this critical stochastic element in a Boltzmann machine. The dynamic cooling effect in simulated annealing can be emulated in this multi-terminal memristive device through electrostatic bias with sigmoidal thresholding distributions. We also show that a machine-learning-based method is efficient for device-circuit co-design of the Boltzmann machine based on the stochastic memristor devices in simulated annealing. The experimental demonstrations of the tunable stochastic memristors combined with the machine-learning-based device-circuit co-optimization approach for stochastic-memristor-based neural-network circuits chart a pathway for the efficient hardware realization of stochastic neural networks with applications in a broad range of electronics and computing disciplines.
Analytical modeling and dynamics of multidomain in metal-ferroelectric-insulator-semiconductor (MFIS)-FETs are presented in this paper. The formation of multi-domain (MD) leads to oscillations in the conduction band in the channel and periodicity in the local electric field in the ferroelectric region. The impact of 2-D local electric field on the MD switching is captured in the model using the domain wall velocity concept. The optimum values of oxide thickness, ferroelectric thickness and channel length are calculated which corresponds to mono-domain device operation. Deviation from the optimum device parameters causes the transition of mono-domain state to multi-domain state in the ferroelectric. This work can be used as a guideline for designing MFIS-NCFETs, which provides the device parameters that leads to monodomain state in the MFIS-NCFET.
This work presents a novel general compact model for 7nm technology node devices like FinFETs. As an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects, the general compact model combining few TCAD calibrated compact models with statistical methods can eliminate the tedious physical derivations. The general compact model has the advantages of efficient extraction, high accuracy, strong scaling capability and excellent transfer capability. As a demo application, two key design knobs of FinFET and their multiple impacts on RC control ESD power clamp circuit are systematically evaluated with implementation of the newly proposed general compact model, accounting for device design, circuit performance optimization and variation control. The performance of ESD power clamp can be improved extremely. This framework is also suitable for pathfinding researches on 5nm node gate-all-around devices, like nanowire (NW) FETs, nanosheet (NSH) FETs and beyond.
Efficient simulation of probabilistic memristors and their networks requires novel modeling approaches. One major departure from the conventional memristor modeling is based on a master equation for the occupation probabilities of network states [arXiv:2003.11011 (2020)]. In the present article, we show how to implement such master equations in SPICE - a general-purpose circuit simulation program. In the case studies, we simulate the dynamics of ac-driven probabilistic binary and multi-state memristors, and dc-driven networks of probabilistic binary and multi-state memristors. Our SPICE results are in perfect agreement with known analytical solutions. Examples of LTspice codes are included.
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