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Register a new userComment on $Phi$ memristor: Real memristor found by F. Z. Wang, L. Li, L. Shi, H. Wu, and L. O. Chua [J. Appl. Phys. 125, 054504 (2019)]
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Wang et al. claim [J. Appl. Phys. 125, 054504 (2019)] that a current-carrying wire interacting with a magnetic core represents a memristor. Here, we demonstrate that this claim is false. We first show that such memristor discovery is based on incorrect physics, which does not even capture basic properties of magnetic core materials, such as their magnetic hysteresis. Moreover, the predictions of Wang et al.s model contradict the experimental curves presented in their paper. Additionally, the theoretical pinched hysteresis loops presented by Wang et al. can not be reproduced if their model is used, and there are serious flaws in their negative memristor emulator design. Finally, a simple gedanken experiment shows that the proposed $Phi$-memristor would fail the memristor test we recently suggested in J. Phys. D: Appl. Phys. 52, 01LT01 (2019). The device discovered by Wang et al. is just an inductor with memory.
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In this reply, we will provide our impersonal, point-to-point responses to the major criticisms (in bold and underlined) in arXiv:1909.12464. Firstly, we will identify a number of (imperceptibly hidden) mistakes in the Comment in understanding/interpreting our physical model. Secondly, we will use a 3rd-party experiment carried out in 1961 (plus other 3rd-party experiments thereafter) to further support our claim that our invented Phi memristor is memristive in spite of the existence of a parasitic inductor effect. Thirdly, we will analyse this parasitic effect mathematically, introduce our work-in-progress (in nanoscale) and point out that this parasitic inductor effect should not become a big worry since it can be completely removed in the macro-scale devices and safely neglected in the nano-scale devices.
Synaptic Sampling Machine (SSM) is a type of neural network model that considers biological unreliability of the synapses. We propose the circuit design of the SSM neural network which is realized through the memristive-CMOS crossbar structure with the synaptic sampling cell (SSC) being used as a basic stochastic unit. The increase in the edge computing devices in the Internet of things era, drives the need for hardware acceleration for data processing and computing. The computational considerations of the processing speed and possibility for the real-time realization pushes the synaptic sampling algorithm that demonstrated promising results on software for hardware implementation.
The superior density of passive analog-grade memristive crossbars may enable storing large synaptic weight matrices directly on specialized neuromorphic chips, thus avoiding costly off-chip communication. To ensure efficient use of such crossbars in neuromorphic computing circuits, variations of current-voltage characteristics of crosspoint devices must be substantially lower than those of memory cells with select transistors. Apparently, this requirement explains why there were so few demonstrations of neuromorphic system prototypes using passive crossbars. Here we report a 64x64 passive metal-oxide memristor crossbar circuit with ~99% device yield, based on a foundry-compatible fabrication process featuring etch-down patterning and low-temperature budget, conducive to vertical integration. The achieved ~26% variations of switching voltages of our devices were sufficient for programming 4K-pixel gray-scale patterns with an average tuning error smaller than 4%. The analog properties were further verified by experimentally demonstrating MNIST pattern classification with a fidelity close to the software-modeled limit for a network of this size, with an ~1% average error of import of ex-situ-calculated synaptic weights. We believe that our work is a significant improvement over the state-of-the-art passive crossbar memories in both complexity and analog properties.
The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25-240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral IO logic in active matrix displays. In this paper, we design and implement a ternary 1-3 line decoder and a ternary 2-9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. We compare our hardware results to a binary coded decimal (BCD)-to-seven segment display decoder, and show our memristor-CMOS approach reduces the total IO power consumption by a factor of approximately 6 times at a maximum synthesizable frequency of 293.77MHz. Although the speed is approximately half of the native built-in BCD-to-seven decoder, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed.
The decay bar B -> bar K* (-> bar K pi) l+ l- offers great opportunities to explore the physics at and above the electroweak scale by means of an angular analysis. We investigate the physics potential of the seven CP asymmetries plus the asymmetry in the rate, working at low dilepton mass using QCD factorization at next-to leading order (NLO). The b ->s CP asymmetries are doubly Cabibbo-suppressed lesssim 1 % in the Standard Model and its extensions where the CKM matrix is the only source of CP violation. Three CP asymmetries are T-odd, and can be O(1) in the presence of non-standard CP violation. The T-even asymmetries can reach O(0.1), limited by the small strong phases in the large recoil region. We furthermore point out an easy way to measure CP phases from time-integrated, untagged bar B_d, B_d -> K* (-> K0 pi0) l+ l- and bar B_s,B_s -> phi (-> K+ K-) l+ l- decays. Analyses of these CP asymmetries can rule out, or further support the minimal description of CP violation through the CKM mechanism. Experimental studies are promising for (super) flavor factories and at hadron colliders.
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