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Register a new userExperimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions
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The recently proposed probabilistic spin logic presents promising solutions to novel computing applications. Multiple cases of implementations, including invertible logic gate, have been studied numerically by simulations. Here we report an experimental demonstration of a magnetic tunnel junction-based hardware implementation of probabilistic spin logic.
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Superparamagnetic tunnel junctions (SMTJs) have emerged as a competitive, realistic nanotechnology to support novel forms of stochastic computation in CMOS-compatible platforms. One of their applications is to generate random bitstreams suitable for use in stochastic computing implementations. We describe a method for digitally programmable bitstream generation based on pre-charge sense amplifiers. This generator is significantly more energy efficient than SMTJ-based bitstream generators that tune probabilities with spin currents and a factor of two more efficient than related CMOS-based implementations. The true randomness of this bitstream generator allows us to use them as the fundamental units of a novel neural network architecture. To take advantage of the potential savings, we codesign the algorithm with the circuit, rather than directly transcribing a classical neural network into hardware. The flexibility of the neural network mathematics allows us to adapt the network to the explicitly energy efficient choices we make at the device level. The result is a convolutional neural network design operating at $approx$ 150 nJ per inference with 97 % performance on MNIST -- a factor of 1.4 to 7.7 improvement in energy efficiency over comparable proposals in the recent literature.
The recent demonstration of current-driven magnetic domain wall logic [Z. Luo et al., Nature 579:214] was based on a three-input logic gate that was identified as a reconfigurable NAND/NOR function. We reinterpret this logic gate as a minority gate within the context of threshold logic, enabling a domain wall threshold logic paradigm in which the device count can be reduced by 80%. Furthermore, by extending the logic gate to more than three inputs of non-equal weight, an 87% reduction in device count can be achieved.
Magnetic tunnel junctions operating in the superparamagnetic regime are promising devices in the field of probabilistic computing, which is suitable for applications like high-dimensional optimization or sampling problems. Further, random number generation is of interest in the field of cryptography. For such applications, a devices uncorrelated fluctuation time-scale can determine the effective system speed. It has been theoretically proposed that a magnetic tunnel junction designed to have only easy-plane anisotropy provides fluctuation rates determined by its easy-plane anisotropy field, and can perform on nanosecond or faster time-scale as measured by its magnetoresistances autocorrelation in time. Here we provide experimental evidence of nanosecond scale fluctuations in a circular shaped easy-plane magnetic tunnel junction, consistent with finite-temperature coupled macrospin simulation results and prior theoretical expectations. We further assess the degree of stochasticity of such signal.
Stochastic spiking neural networks based on nanoelectronic spin devices can be a possible pathway to achieving brainlike compact and energy-effcient cognitive intelligence. The computational model attempt to exploit the intrinsic device stochasticity of nanoelectronic synaptic or neural components to perform learning or inference. However, there has been limited analysis on the scaling effect of stochastic spin devices and its impact on the operation of such stochastic networks at the system level. This work attempts to explore the design space and analyze the performance of nanomagnet-based stochastic neuromorphic computing architectures for magnets with different barrier heights. We illustrate how the underlying network architecture must be modified to account for the random telegraphic switching behavior displayed by magnets with low barrier heights as they are scaled into the superparamagnetic regime. We perform a device-to-system-level analysis on a deep neural-network architecture for a digit-recognition problem on the MNIST data set.
Featuring low heat dissipation, devices based on spin-wave logic gates promise to comply with increasing future requirements in information processing. In this work, we present the experimental realization of a majority gate based on the interference of spin waves in an Yttrium-Iron-Garnet-based waveguiding structure. This logic device features a three-input combiner with the logic information encoded in the phase of the spin waves. We show that the phase of the output signal represents the majority of the phase of the input signals. A switching time of about 10 ns in the prototype device provides evidence for the ability of sub-nanosecond data processing in future down-scaled devices.
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