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Register a new userCryogenic Memory Architecture Integrating Spin Hall Effect based Magnetic Memory and Superconductive Cryotron Devices
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One of the most challenging obstacles to realizing exascale computing is minimizing the energy consumption of L2 cache, main memory, and interconnects to that memory. For promising cryogenic computing schemes utilizing Josephson junction superconducting logic, this obstacle is exacerbated by the cryogenic system requirements that expose the technologys lack of high-density, high-speed and power-efficient memory. Here we demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below $10^{-6}$, and a 4x4 array can be fully addressed with bit select error rates of $10^{-6}$. This demonstration is a first step towards a full cryogenic memory architecture targeting energy and performance specifications appropriate for applications in superconducting high performance and quantum computing control systems, which require significant memory resources operating at 4 K.
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The interplay between ferromagnetism and topological properties of electronic band structures leads to a precise quantization of Hall resistance without any external magnetic field. This so-called quantum anomalous Hall effect (QAHE) is born out of topological correlations, and is oblivious of low-sample quality. It was envisioned to lead towards dissipationless and topologically protected electronics. However, no clear framework of how to design such an electronic device out of it exists. Here we construct an ultra-low power, non-volatile, cryogenic memory architecture leveraging the QAHE phenomenon. Our design promises orders of magnitude lower cell area compared with the state-of-the-art cryogenic memory technologies. We harness the fundamentally quantized Hall resistance levels in moire graphene heterostructures to store non-volatile binary bits (1, 0). We perform the memory write operation through controlled hysteretic switching between the quantized Hall states, using nano-ampere level currents with opposite polarities. The non-destructive read operation is performed by sensing the polarity of the transverse Hall voltage using a separate pair of terminals. We custom design the memory architecture with a novel sensing mechanism to avoid accidental data corruption, ensure highest memory density and minimize array leakage power. Our design is transferrable to any material platform exhibiting QAHE, and provides a pathway towards realizing topologically protected memory devices.
The operation of resistive and phase-change memory (RRAM and PCM) is controlled by highly localized self-heating effects, yet detailed studies of their temperature are rare due to challenges of nanoscale thermometry. Here we show that the combination of Raman thermometry and scanning thermal microscopy (SThM) can enable such measurements with high spatial resolution. We report temperature-dependent Raman spectra of HfO$_2$, TiO$_2$ and Ge$_2$Sb$_2$Te$_5$ (GST) films, and demonstrate direct measurements of temperature profiles in lateral PCM devices. Our measurements reveal that electrical and thermal interfaces dominate the operation of such devices, uncovering a thermal boundary resistance of 30 m$^2$K$^{-1}$GW$^{-1}$ at GST-SiO$_2$ interfaces and an effective thermopower 350 $mu$V/K at GST-Pt interfaces. We also discuss possible pathways to apply Raman thermometry and SThM techniques to nanoscale and vertical resistive memory devices.
Josephson junctions containing two ferromagnetic layers are being considered for use in cryogenic memory. Our group recently demonstrated that the ground-state phase difference across such a junction with carefully chosen layer thicknesses could be controllably toggled between zero and $pi$ by switching the relative magnetization directions of the two layers between the antiparallel and parallel configurations. However, several technological issues must be addressed before those junctions can be used in a large-scale memory. Many of these issues can be more easily studied in single junctions, rather than in the Superconducting QUantum Interference Device (SQUID) used for the phase-sensitive measurements. In this work, we report a comprehensive study of spin-valve junctions containing a Ni layer with a fixed thickness of 2.0 nm, and a NiFe layer of thickness varying between 1.1 and 1.8 nm in steps of 0.1 nm. We extract the field shift of the Fraunhofer patterns and the critical currents of the junctions in the parallel and antiparallel magnetic states, as well as the switching fields of both magnetic layers. We also report a partial study of similar junctions containing a slightly thinner Ni layer of 1.6 nm and the same range of NiFe thicknesses. These results represent the first step toward mapping out a ``phase diagram for phase-controllable spin-valve Josephson junctions as a function of the two magnetic layer thicknesses.
Race logic is a relative timing code that represents information in a wavefront of digital edges on a set of wires in order to accelerate dynamic programming and machine learning algorithms. Skyrmions, bubbles, and domain walls are mobile magnetic configurations (solitons) with applications for Boolean data storage. We propose to use current-induced displacement of these solitons on magnetic racetracks as a native temporal memory for race logic computing. Locally synchronized racetracks can spatially store relative timings of digital edges and provide non-destructive read-out. The linear kinematics of skyrmion motion, the tunability and low-voltage asynchronous operation of the proposed device, and the elimination of any need for constant skyrmion nucleation make these magnetic racetracks a natural memory for low-power, high-throughput race logic applications.
Development of memory devices with ultimate performance has played a key role in innovation of modern electronics. As a mainstream technology nonvolatile memory devices have manifested high capacity and mechanical reliability, however current major bottlenecks include low extinction ratio and slow operational speed. Although substantial effort has been employed to improve their performance, a typical hundreds of micro- or even milli- second write time remains a few orders of magnitude longer than their volatile counterparts. We have demonstrated nonvolatile, floating-gate memory devices based on van der Waals heterostructures with atomically sharp interfaces between different functional elements, and achieved ultrahigh-speed programming/erasing operations verging on an ultimate theoretical limit of nanoseconds with extinction ratio up to 10^10. This extraordinary performance has allowed new device capabilities such as multi-bit storage, thus opening up unforeseen applications in the realm of modern nanoelectronics and offering future fabrication guidelines for device scale-up.
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