Subscribe to the gold package and get unlimited access to Shamra Academy
Register a new userClifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies
97
0
0.0
(
0
)
Ask ChatGPT about the research
No Arabic abstract
Clifford gates play a role in the optimisation of Clifford+T circuits. Reducing the count and the depth of Clifford gates, as well as the optimal scheduling of T gates, influence the hardware and the time costs of executing quantum circuits. This work focuses on circuits protected by the surface quantum error-correcting code. The result of compiling a quantum circuit for the surface code is called a topological assembly. We use queuing theory to model a part of the compiled assemblies, evaluate the models, and make the empiric observation that at least for certain Clifford+T circuits (e.g. adders), the assemblys execution time does not increase when the available hardware is restricted. This is an interesting property, because it shows that T gate scheduling and Clifford gate optimisation have the potential to save both hardware and execution time.
rate research
Read More
Surface quantum error-correcting codes are the leading proposal for fault-tolerance within quantum computers. We present OpenSurgery, a scalable tool for the preparation of circuits protected by the surface code operated through lattice surgery. Lattice surgery is considered a resource efficient method to implement surface code computations. Resource efficiency refers to the number of physical qubits and the time necessary for executing a quantum computation. OpenSurgery is a first step towards methods that aid quantum algorithm design informed by the realities of the hardware architectures. OpenSurgery can: 1) lay out arbitrary quantum circuits, 2) estimate the quantum resources used for their execution, 3) visualise the resulting 3D topological assemblies. Source code is available at http://www.github.com/alexandrupaler/opensurgery.
One of the main challenges for quantum computation is that while the number of gates required to perform a non-trivial quantum computation may be very large, decoherence and errors in realistic quantum architectures limit the number of physical gate operations that can be performed coherently. Therefore, an optimal mapping of the quantum algorithm into the physically available set of operations is of crucial importance. We examine this problem for a measurement-only topological quantum computer based on Majorana zero modes, where gates are performed through sequences of measurements. Such a scheme has been proposed as a practical, scalable approach to process quantum information in an array of topological qubits built using Majorana zero modes. Building on previous work that has shown that multi-qubit Clifford gates can be enacted in a topologically protected fashion in such qubit networks, we discuss methods to obtain the optimal measurement sequence for a given Clifford gate under the constraints imposed by the physical architecture, such as layout and the relative difficulty of implementing different types of measurements. Our methods also provide tools for comparative analysis of different architectures and strategies, given experimental characterizations of particular aspects of the systems under consideration. As a further non-trivial demonstration, we discuss an implementation of the surface code in Majorana-based topological qubits. We use the techniques developed here to obtain an optimized measurement sequence that implements the stabilizer measurements using only fermionic parity measurements on nearest-neighbor topological qubit islands.
For universal quantum computation, a major challenge to overcome for practical implementation is the large amount of resources required for fault-tolerant quantum information processing. An important aspect is implementing arbitrary unitary operators built from logical gates within the quantum error correction code. A synthesis algorithm can be used to approximate any unitary gate up to arbitrary precision by assembling sequences of logical gates chosen from a small set of universal gates that are fault-tolerantly performable while encoded in a quantum error-correction code. However, current procedures do not yet support individual assignment of base gate costs and many do not support extended sets of universal base gates. We analysed cost-optimal sequences using an exhaustive search based on Dijkstras pathfinding algorithm for the canonical Clifford+$T$ set of base gates and compared them to when additionally including $Z$-rotations from higher orders of the Clifford hierarchy. Two approaches of assigning base gate costs were used. First, costs were reduced to $T$-counts by recursively applying a $Z$-rotation catalyst circuit. Second, costs were assigned as the average numbers of raw (i.e. physical level) magic states required to directly distil and implement the gates fault-tolerantly. We found that the average sequence cost decreases by up to $54pm 3%$ when using the $Z$-rotation catalyst circuit approach and by up to $33pm 2 %$ when using the magic state distillation approach. In addition, we investigated observed limitations of certain assignments of base gate costs by developing an analytic model to estimate the proportion of sets of $Z$-rotation gates from higher orders of the Clifford hierarchy that are found within sequences approximating random target gates.
To achieve scalable quantum computing, improving entangling-gate fidelity and its implementation-efficiency are of utmost importance. We present here a linear method to construct provably power-optimal entangling gates on an arbitrary pair of qubits on a trapped-ion quantum computer. This method leverages simultaneous modulation of amplitude, frequency, and phase of the beams that illuminate the ions and, unlike the state of the art, does not require any search in the parameter space. The linear method is extensible, enabling stabilization against external parameter fluctuations to an arbitrary order at a cost linear in the order. We implement and demonstrate the power-optimal, stabilized gate on a trapped-ion quantum computer.
Fault-tolerant logic gates will consume a large proportion of the resources of a two-dimensional quantum computing architecture. Here we show how to perform a fault-tolerant non-Clifford gate with the surface code; a quantum error-correcting code now under intensive development. This alleviates the need for distillation or higher-dimensional components to complete a universal gate set. The operation uses both local transversal gates and code deformations over a time that scales with the size of the qubit array. An important component of the gate is a just-in-time decoder. These decoding algorithms allow us to draw upon the advantages of three-dimensional models using only a two-dimensional array of live qubits. Our gate is completed using parity checks of weight no greater than four. We therefore expect it to be amenable with near-future technology. As the gate circumvents the need for magic-state distillation, it may reduce the resource overhead of surface-code quantum computation considerably.
Log in to be able to interact and post comments
comments
Fetching comments
Sign in to be able to follow your search criteria
