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Register a new userThe ESS FPGA Framework and its Application on the ESS LLRF System
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The functions of the Low-Level Radio Frequency (LLRF) system at European Spallation Source (ESS) are implemented on different Field-Programmable Gate Array (FPGA) boards in a Micro Telecommunications Computing Architecture (MTCA) crate. Besides the algorithm, code that provides access to the peripherals connected to the FPGA is necessary. In order to provide a common platform for the FPGA developments at ESS - the ESS FPGA Framework has been designed. The framework facilitates the integration of different algorithms on different FPGA boards. Three functions are provided by the framework: (1) Communication interfaces to peripherals, e.g. Analog-to-Digital Converters (ADCs) and on-board memory, (2) Upstream communication with the control system over Peripheral Component Interconnect Express (PCIe), and (3) Configuration of the on-board peripherals. To keep the framework easily extensible by Intellectual Property (IP) blocks and to enable seamless integration with the Xilinx design tools, the Advanced eXtensible Interface version 4 (AXI4) bus is the chosen communication interconnect. Furthermore, scripts automatize the building of the FPGA configuration, software components and the documentation. The LLRF control algorithms have been successfully integrated into the framework.
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The ambitious instrument suite for the future European Spallation Source whose civil construction started recently in Lund, Sweden, demands a set of diverse and challenging requirements for the neutron detectors. For instance, the unprecedented high flux expected on the samples to be investigated in neutron diffraction or reflectometry experiments requires detectors that can handle high counting rates, while the investigation of sub-millimeter protein crystals will only be possible with large-area detectors that can achieve a position resolution as low as 200 {mu}m. This has motivated an extensive research and development campaign to advance the state-of-the-art detector and to find new technologies that can reach maturity by the time the ESS will operate at full potential. This paper presents the key detector requirements for three of the Time-of-Flight diffraction instrument concepts selected by the Scientific Advisory Committee to advance into the phase of preliminary engineering design. We discuss the available detector technologies suitable for this particular instrument class and their major challenges. The detector technologies selected by the instrument teams to collect the diffraction patterns are briefly discussed. Analytical calculations, Monte-Carlo simulations, and real experimental data are used to develop a generic method to esti- mate the event rate in the diffraction detectors. The proposed approach is based upon conservative assumptions that use information and input parameters that reflect our current level of knowledge and understanding of the ESS project. We apply this method to make predictions for the future diffraction instruments, and thus provide additional information that can help the instrument teams with the optimisation of the detector designs.
The HIBEAM/NNBAR program is a proposed two-stage experiment at the European Spallation Source focusing on searches for baryon number violation via processes in which neutrons convert to antineutrons. This paper outlines the computing and detector simulation framework for the HIBEAM/NNBAR program. The simulation is based on predictions of neutron flux and neutronics together with signal and background generation. A range of diverse simulation packages are incorporated, including Monte Carlo transport codes, neutron ray-tracing simulation packages, and detector simulation software. The common simulation package in which these elements are interfaced together is discussed. Data management plans and triggers are also described.
The aim of this short note is to present an option for a source of ultracold neutrons (UCNs), which could profit from the pulse time-structure of the future ESS spallation neutron source in Lund, and thus which could produce a very high UCN density and a rather high UCN flux simultaneously. In order to realize this idea one has to install a relatively thin solid-deuterium UCN source in a close vicinity to the spallation target and to couple it with an extraction UCN guide with an entrance membrane window, which is moving periodically and synchronously with the operation cycle of the spallation source, as explained in the text below. This proposal profits from the fact that all characteristic parameters of the problem, such as the pulse duration of the ESS spallation source, the typical thickness of solid deuterium source that could be easily realized, the typical time of generation of UCNs in solid deuterium, the length and diameter of the extraction neutron guide and the time diagram of the membrane motion that is still realistic, they all fit nicely to optimum desired parameters. The UCN density produced in such a way could approach 10^6 UCN/cm3.
A sensitive search for neutron-antineutron oscillations can provide a unique probe of some of the central questions in particle physics and cosmology: the energy scale and mechanism for baryon number violation, the origin of the baryon-antibaryon asymmetry of the universe, and the mechanism for neutrino mass generation. A remarkable opportunity has emerged to search for such oscillations with the construction of the European Spallation Source (ESS). A collaboration has been formed which has proposed a search at the ESS, which would provide a sensitivity to the oscillation probability which is three orders of magnitude greater than that achieved at an ILL experiment at which the present best limit on free neutron-antineutron oscillations was obtained.
Waveform feature is one of the requirements for the FRIB LLRF controllers. It is desired that the LLRF con-trollers store the internal data (e.g. the amplitude and phase information of forward/reverse/cavity signals) for at least one second of sampled data at the RF feedback control loop rate (around 1.25 MHz). One use case is to freeze the data buffer when an interlock event happens and read out the fast data to diagnose the problem. An-other use case is to monitor a set of signals at a decimated rate (user settable) while the data buffer is still running, like using an oscilloscope. The detailed implementation will be discussed in the paper, including writing data into the DDR memory through the native interface, reading out the data through the bus interface, etc.
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