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Register a new userNanosurveyor: a framework for real-time data processing
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Scientists are drawn to synchrotrons and accelerator based light sources because of their brightness, coherence and flux. The rate of improvement in brightness and detector technology has outpaced Moores law growth seen for computers, networks, and storage, and is enabling novel observations and discoveries with faster frame rates, larger fields of view, higher resolution, and higher dimensionality. Here we present an integrated software/algorithmic framework designed to capitalize on high throughput experiments, and describe the streamlined processing pipeline of ptychography data analysis. The pipeline provides throughput, compression, and resolution as well as rapid feedback to the microscope operators.
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One of the optimization goals of a particle accelerator is to reach the highest possible beam peak current. For that to happen the electron bunch propagating through the accelerator should be kept relatively short along the direction of its travel. In order to obtain a better understanding of the beam composition it is crucial to evaluate the electric charge distribution along the micrometer-scale packets. The task of the Electro-Optic Detector (EOD) is to imprint the beam charge profile on the spectrum of light of a laser pulse. The actual measurement of charge distribution is then extracted with a spectrometer based on a diffraction grating. The article focuses on developed data acquisition and processing system called the High-speed Optical Line Detector (HOLD). It is a 1D image acquisition system which solves several challenges related to capturing, buffering, processing and transmitting large data streams with use of the FPGA device. It implements a latency-optimized custom architecture based on the AXI interfaces. The HOLD device is realized as an FPGA Mezzanine Card (FMC) carrier with single High Pin-Count connector hosting the KIT KALYPSO detector. The solution presented in the paper is probably one of the world fastest line cameras. Thanks to its custom architecture it is capable of capturing at least 10 times more frames per second than fastest comparable commercially available devices.
With the next-generation Timepix3 hybrid pixel detector, new possibilities and challenges have arisen. The Timepix3 segments active sensor area of 1.98 $cm^2$ into a square matrix of 256 x 256 pixels. In each pixel, the Time of Arrival (ToA, with a time binning of 1.56 $ns$) and Time over Threshold (ToT, energy) are measured simultaneously in a data-driven, i.e. self-triggered, read-out scheme. This contribution presents a framework for data acquisition, real-time clustering, visualization, classification and data saving. All of these tasks can be performed online, directly from multiple readouts through UDP protocol. Clusters are reconstructed on a pixel-by-pixel decision from the stream of not-necessarily chronologically sorted pixel data. To achieve quick spatial pixel-to-cluster matching, non-trivial data structures (quadtree) are utilized. Furthermore, parallelism (i.e multi-threaded architecture) is used to further improve the performance of the framework. Such real-time clustering offers the advantages of online filtering and classification of events. Versatility of the software is ensured by supporting all major operating systems (macOS, Windows and Linux) with both graphical and command-line interfaces. The performance of the real-time clustering and applied filtration methods are demonstrated using data from the Timepix3 network installed in the ATLAS and MoEDAL experiments at CERN.
A novel approach to tomographic data processing has been developed and evaluated using the Jagiellonian PET (J-PET) scanner as an example. We propose a system in which there is no need for powerful, local to the scanner processing facility, capable to reconstruct images on the fly. Instead we introduce a Field Programmable Gate Array (FPGA) System-on-Chip (SoC) platform connected directly to data streams coming from the scanner, which can perform event building, filtering, coincidence search and Region-Of-Response (ROR) reconstruction by the programmable logic and visualization by the integrated processors. The platform significantly reduces data volume converting raw data to a list-mode representation, while generating visualization on the fly.
The High Level Trigger (HLT) system of the ALICE experiment is an online event filter and trigger system designed for input bandwidths of up to 25 GB/s at event rates of up to 1 kHz. The system is designed as a scalable PC cluster, implementing several hundred nodes. The transport of data in the system is handled by an object-oriented data flow framework operating on the basis of the publisher-subscriber principle, being designed fully pipelined with lowest processing overhead and communication latency in the cluster. In this paper, we report the latest measurements where this framework has been operated on five different sites over a global north-south link extending more than 10,000 km, processing a ``real-time data flow.
Small animal Positron Emission Tomography (PET) is dedicated to small animal imaging, which requires high position and energy precision, as well as good flexibility and efficiency of the electronics. This paper presents the design of a digital signal processing logic for a marmoset brain PET system based on LYSO crystal arrays, SiPMs, and the resistive network readout method. We implement 32-channel signal processing in a single Xilinx Artix-7 Field-Programmable Gate Array (FPGA). The logic is designed to support four online modes which are regular data processing mode, flood map construction mode, energy spectrum construction mode, and raw data mode. Several functions are integrated, including two-dimensional (2D) raw position calculation, crystal locating, events filtering, and synchronization detection. Furthermore, a series of online corrections is also integrated, such as photon peak correction to 511 keV and time measurement result correction with crystal granularity. A Gigabit Ethernet interface is utilized for data transfer, Look-Up Tables (LUTs) configuration, and command issuing. The pipeline logic works at 125 MHz with a signal processing capability beyond the required data rate of 1,000,000 events/s/channel. A series of initial tests are conducted. The results indicate that the logic design meets the application requirement.
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