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Register a new userSaving Moores Law Down To 1nm Channels With Anisotropic Effective Mass
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Added by
Hesameddin Ilatikhameneh
Publication date
2016
fields
Physics
and research's language is
English
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Scaling transistors dimensions has been the thrust for the semiconductor industry in the last 4 decades. However, scaling channel lengths beyond 10 nm has become exceptionally challenging due to the direct tunneling between source and drain which degrades gate control, switching functionality, and worsens power dissipation. Fortunately, the emergence of novel classes of materials with exotic properties in recent times has opened up new avenues in device design. Here, we show that by using channel materials with an anisotropic effective mass, the channel can be scaled down to 1nm and still provide an excellent switching performance in both MOSFETs and TFETs. In the case of TFETs, a novel design has been proposed to take advantage of anisotropic mass in both ON- and OFF-state of the TFETs. Full-band atomistic quantum transport simulations of phosphorene nanoribbon MOSFETs and TFETs based on the new design have been performed as a proof.
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We report measurements of the spin susceptibility in dilute (rs up to 10) AlAs two-dimensional (2D) electrons occupying a single conduction-band valley with an anisotropic in-plane Fermi contour, characterized by longitudinal and transverse effective masses, ml and mt. As the density is decreased, the spin susceptibility is significantly enhanced over its band value, reflecting the role of interaction. Yet the enhancement is suppressed compared to the results of quantum Monte Carlo based calculations that take the finite thickness of the electron layer into account but assume an isotropic effective mass equal to sqrt(ml.mt). Proper treatment of an interacting 2D system with an anisotropic effective mass therefore remains a theoretical challenge.
As an emerging technology, blockchain has achieved great success in numerous application scenarios, from intelligent healthcare to smart cities. However, a long-standing bottleneck hindering its further development is the massive resource consumption attributed to the distributed storage and computation methods. This makes blockchain suffer from insufficient performance and poor scalability. Here, we analyze the recent blockchain techniques and demonstrate that the potential of widely-adopted consensus-based scaling is seriously limited, especially in the current era when Moores law-based hardware scaling is about to end. We achieve this by developing an open-source benchmarking tool, called Prism, for investigating the key factors causing low resource efficiency and then discuss various topology and hardware innovations which could help to scale up blockchain. To the best of our knowledge, this is the first in-depth study that explores the next-generation scaling strategies by conducting large-scale and comprehensive benchmarking.
The inability of Moores Law and other figure-of-merits (FOMs) to accurately explain the technology development of the semiconductor industry demands a holistic merit to guide the industry. Here we introduce a FOM termed CLEAR that accurately postdicts technology developments since the 1940s until today, and predicts photonics as a logical extension to keep-up the pace of information-handling machines. We show that CLEAR (Capability-to-Latency-Energy-Amount-Resistance) is multi-hierarchical applying to the device, interconnect, and system level. Being a holistic FOM, we show that empirical trends such as Moores Law and the Makimotos wave are special cases of the universal CLEAR merit. Looking ahead, photonic board- and chip-level technologies are able to continue the observed doubling rate of the CLEAR value every 12 months, while electronic technologies are unable to keep pace.
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3D integration, i.e., stacking of integrated circuit layers using parallel or sequential processing is gaining rapid industry adoption with the slowdown of Moores law scaling. 3D stacking promises potential gains in performance, power and cost but the actual magnitude of gains varies depending on end-application, technology choices and design. In this talk, we will discuss some key challenges associated with 3D design and how design-for-3D will require us to break traditional silos of micro-architecture, circuit/physical design and manufacturing technology to work across abstractions to enable the gains promised by 3D technologies.
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