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Register a new userInterfacial thermal conductance across metal-insulator/semiconductor interfaces due to surface states
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We point out that the effective channel for the interfacial thermal conductance, the inverse of Kapitza resistance, of metal-insulator/semiconductor interfaces is governed by the electron-phonon interaction mediated by the surface states allowed in a thin region near the interface. Our detailed calculations demonstrate that the interfacial thermal conductance across Pb/Pt/Al/Au-diamond interfaces are only slightly different among these metals, and reproduce well the experimental results of the interfacial thermal conductance across metal-diamond interfaces observed by Stoner et al. [Phys. Rev. Lett. 68, 1563 (1992)] and most recently by Hohensee et al. [Nature Commun. 6, 6578 (2015)].
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The wide bandgap, high-breakdown electric field, and high carrier mobility makes GaN an ideal material for high-power and high-frequency electronics applications such as wireless communication and radar systems. However, the performance and reliability of GaN-based HEMTs are limited by the high channel temperature induced by Joule-heating in the device channel. High thermal conductivity substrates integrated with GaN can improve the extraction of heat from GaN based HEMTs and lower the device operating temperature. However, heterogeneous integration of GaN with diamond substrates is not trivial and presents technical challenges to maximize the heat dissipation potential brought by the diamond substrate. In this work, two modified room temperature surface activated bonding techniques are used to bond GaN and single crystal diamond with different interlayer thicknesses. TDTR is used to measure the thermal properties from room temperature to 480 K. A relatively large TBC of the GaN-diamond interfaces with a 4nm interlayer was observed and material characterization was performed to link the structure of the interface to the TBC. Device modeling shows that the measured GaN-diamond TBC values obtained from bonding can enable high power GaN devices by taking the full advantage of the high thermal conductivity of single crystal diamond and achieve excellent cooling effect. Furthermore, the room-temperature bonding process in this work do not induce stress problem due to different coefficient of thermal expansion in other high temperature integration processes in previous studies. Our work sheds light on the potential for room-temperature heterogeneous integration of semiconductors with diamond for applications of electronics cooling especially for GaN-on-diamond devices.
GaN-based HEMTs have the potential to be widely used in high-power and high-frequency electronics while their maximum output powers are limited by high channel temperature induced by near-junction Joule-heating, which degrades device performance and reliability. Increasing the TBC between GaN and SiC will aid in the heat dissipation of GaN-on-SiC power devices, taking advantage of the high thermal conductivity of the SiC substrate. However, a good understanding of the TBC of this technically important interface is still lacking due to the complicated nature of interfacial heat transport. In this work, a lattice-mismatch-insensitive surface activated bonding method is used to bond GaN directly to SiC and thus eliminating the AlN layer altogether. This allows for the direct integration of high quality GaN layers with SiC to create a high thermal boundary conductance interface. TDTR is used to measure the thermal properties of the GaN thermal conductivity and GaN-SiC TBC. The measured GaN thermal conductivity is larger than that of GaN grown by MBE on SiC, showing the impact of reducing the dislocations in the GaN near the interface. High GaN-SiC TBC is observed for the bonded GaN-SiC interfaces, especially for the annealed interface whose TBC (230 MW/m2-K) is close to the highest values ever reported. To understand the structure-thermal property relation, STEM and EELS are used to characterize the interface structure. The results show that, for the as-bonded sample, there exists an amorphous layer near the interface for the as bonded samples. This amorphous layer is crystallized upon annealing, leading to the high TBC found in our work. Our work paves the way for thermal transport across bonded interfaces, which will impact real-world applications of semiconductor integration and packaging.
The existed theories and methods for calculating interfacial thermal conductance of solid-solid interface lead to diverse values that deviate from experimental measurements. In this letter, We propose a model to estimate the ITC at high temperature without comprehensive calculations, where the interface between two dissimilar solids can be treated as an amorphous thin layer and the coordination number density across interface becomes a key parameter. Our model predicts that the ITCs of various interfaces at 300K are in a narrow range: 10$^{7}$W m$^{-2}$K$^{-1}$ $sim $10$^{9}$ W m$^{-2}$ K$^{-1}$, which is in good agreement with the experimental measurement.
The semiconductor-metal junction is one of the most critical factors for high performance electronic devices. In two-dimensional (2D) semiconductor devices, minimizing the voltage drop at this junction is particularly challenging and important. Despite numerous studies concerning contact resistance in 2D semiconductors, the exact nature of the buried interface under a three-dimensional (3D) metal remains unclear. Herein, we report the direct measurement of electrical and optical responses of 2D semiconductor-metal buried interfaces using a recently developed metal-assisted transfer technique to expose the buried interface which is then directly investigated using scanning probe techniques. We characterize the spatially varying electronic and optical properties of this buried interface with < 20 nm resolution. To be specific, potential, conductance and photoluminescence at the buried metal/MoS2 interface are correlated as a function of a variety of metal deposition conditions as well as the type of metal contacts. We observe that direct evaporation of Au on MoS2 induces a large strain of ~5% in the MoS2 which, coupled with charge transfer, leads to degenerate doping of the MoS2 underneath the contact. These factors lead to improvement of contact resistance to record values of 138 kohm-um, as measured using local conductance probes. This approach was adopted to characterize MoS2-In/Au alloy interfaces, demonstrating contact resistance as low as 63 kohm-um. Our results highlight that the MoS2/Metal interface is sensitive to device fabrication methods, and provides a universal strategy to characterize buried contact interfaces involving 2D semiconductors.
Thermal transport properties at the metal/MoS2 interfaces are analyzed by using an atomistic phonon transport model based on the Landauer formalism and first-principles calculations. The considered structures include chemisorbed Sc(0001)/MoS2 and Ru(0001)/MoS2, physisorbed Au(111)/MoS2, as well as Pd(111)/MoS2 with intermediate characteristics. Calculated results illustrate a distinctive dependence of thermal transfer on the details of interfacial microstructures. More specifically, the chemisorbed case with a stronger bonding exhibits a generally smaller interfacial thermal resistance than the physisorbed. Comparison between metal/MoS2 and metal/graphene systems suggests that metal/MoS2 is significantly more resistive. Further examination of lattice dynamics identifies the presence of multiple distinct atomic planes and bonding patterns at the interface as the key origin of the observed large thermal resistance.
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