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Exact synthesis is a tool used in algorithms for approximating an arbitrary qubit unitary with a sequence of quantum gates from some finite set. These approximation algorithms find asymptotically optimal approximations in probabilistic polynomial time, in some cases even finding the optimal solution in probabilistic polynomial time given access to an oracle for factoring integers. In this paper, we present a common mathematical structure underlying all results related to the exact synthesis of qubit unitaries known to date, including Clifford+T, Clifford-cyclotomic and V-basis gate sets, as well as gates sets induced by the braiding of Fibonacci anyons in topological quantum computing. The framework presented here also provides a means to answer questions related to the exact synthesis of unitaries for wide classes of other gate sets, such as Clifford+T+V and SU(2) level k anyons.
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We present an algorithm for efficiently approximating of qubit unitaries over gate sets derived from totally definite quaternion algebras. It achieves $varepsilon$-approximations using circuits of length $O(log(1/varepsilon))$, which is asymptotically optimal. The algorithm achieves the same quality of approximation as previously-known algorithms for Clifford+T [arXiv:1212.6253], V-basis [arXiv:1303.1411] and Clifford+$pi/12$ [arXiv:1409.3552], running on average in time polynomial in $O(log(1/varepsilon))$ (conditional on a number-theoretic conjecture). Ours is the first such algorithm that works for a wide range of gate sets and provides insight into what should constitute a good gate set for a fault-tolerant quantum computer.
We present a synthesis framework to map logic networks into quantum circuits for quantum computing. The synthesis framework is based on LUT networks (lookup-table networks), which play a key role in conventional logic synthesis. Establishing a connection between LUTs in a LUT network and reversible single-target gates in a reversible network allows us to bridge conventional logic synthesis with logic synthesis for quantum computing, despite several fundamental differences. We call our synthesis framework LUT-based Hierarchical Reversible Logic Synthesis (LHRS). Input to LHRS is a classical logic network; output is a quantum network (realized in terms of Clifford+$T$ gates). The framework offers to trade-off the number of qubits for the number of quantum gates. In a first step, an initial network is derived that only consists of single-target gates and already completely determines the number of qubits in the final quantum network. Different methods are then used to map each single-target gate into Clifford+$T$ gates, while aiming at optimally using available resources. We demonstrate the effectiveness of our method in automatically synthesizing IEEE compliant floating point networks up to double precision. As many quantum algorithms target scientific simulation applications, they can make rich use of floating point arithmetic components. But due to the lack of quantum circuit descriptions for those components, it can be difficult to find a realistic cost estimation for the algorithms. Our synthesized benchmarks provide cost estimates that allow quantum algorithm designers to provide the first complete cost estimates for a host of quantum algorithms. Thus, the benchmarks and, more generally, the LHRS framework are an essential step towards the goal of understanding which quantum algorithms will be practical in the first generations of quantum computers.
To bridge the gap between limited hardware access and the huge demand for experiments for Noisy Intermediate-Scale Quantum (NISQ) computing system study, a simulator which can capture the modeling of both the quantum processor and its classical control system to realize early-stage evaluation and design space exploration, is naturally invoked but still missing. This paper presents SANQ, a Simulation framework for Architecting NISQ computing system. SANQ consists of two components, 1) an optimized noisy quantum computing (QC) simulator with flexible error modeling accelerated by eliminating redundant computation, and 2) an architectural simulation infrastructure to construct behavior models for evaluating the control systems. SANQ is validated with existing NISQ quantum processor and control systems to ensure simulation accuracy. It can capture the variance on the QC device and simulate the timing behavior precisely (<1% and 10% error for various real control systems). Several potential applications are proposed to show that SANQ could benefit the future design of NISQ compiler, architecture, etc.
Quantum resource analysis is crucial for designing quantum circuits as well as assessing the viability of arbitrary (error-corrected) quantum computations. To this end, we introduce QUANTIFY, which is an open-source framework for the quantitative analysis of quantum circuits. It is based on Google Cirq and is developed with Clifford+T circuits in mind, and it includes the necessary methods to handle Toffoli+H and more generalised controlled quantum gates, too. Key features of QUANTIFY include: (1) analysis and optimisation methods which are compatible with the surface code, (2) choice between different automated (mixed polarity) Toffoli gate decompositions, (3) semi-automatic quantum circuit rewriting and quantum gate insertion methods that take into account known gate commutation rules, and (4) novel optimiser types that can be combined with different verification methods (e.g. truth table or circuit invariants like number of wires). For benchmarking purposes QUANTIFY includes quantum memory and quantum arithmetic circuits. Experimental results show that the frameworks performance scales to circuits with thousands of qubits.
We review some of the features of the ProjectQ software framework and quantify their impact on the resulting circuits. The concise high-level language facilitates implementing even complex algorithms in a very time-efficient manner while, at the same time, providing the compiler with additional information for optimization through code annotation - so-called meta-instructions. We investigate the impact of these annotations for the example of Shors algorithm in terms of logical gate counts. Furthermore, we analyze the effect of different intermediate gate sets for optimization and how the dimensions of the resulting circuit depend on a smart choice thereof. Finally, we demonstrate the benefits of a modular compilation framework by implementing mapping procedures for one- and two-dimensional nearest neighbor architectures which we then compare in terms of overhead for different problem sizes.
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