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Nanoscale integrated photonic devices and circuits offer a path to ultra-low power computation at the few-photon level. Here we propose an optical circuit that performs a ubiquitous operation: the controlled, random-access readout of a collection of stored memory phases or, equivalently, the computation of the inner product of a vector of phases with a binary selector vector, where the arithmetic is done modulo 2pi and the result is encoded in the phase of a coherent field. This circuit, a collection of cascaded interferometers driven by a coherent input field, demonstrates the use of coherence as a computational resource, and of the use of recently-developed mathematical tools for modeling optical circuits with many coupled parts. The construction extends in a straightforward way to the computation of matrix-vector and matrix-matrix products, and, with the inclusion of an optical feedback loop, to the computation of a weighted readout of stored memory phases. We note some applications of these circuits for error correction and for computing tasks requiring fast vector inner products, e.g. statistical classification and some machine learning algorithms.
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We present some basic integer arithmetic quantum circuits, such as adders and multipliers-accumulators of various forms, as well as diagonal operators, which operate on multilevel qudits. The integers to be processed are represented in an alternative basis after they have been Fourier transformed. Several arithmetic circuits operating on Fourier transformed integers have appeared in the literature for two level qubits. Here we extend these techniques on multilevel qudits, as they may offer some advantages relative to qubits implementations. The arithmetic circuits presented can be used as basic building blocks for higher level algorithms such as quantum phase estimation, quantum simulation, quantum optimization etc., but they can also be used in the implementation of a quantum fractional Fourier transform as it is shown in a companion work presented separately.
We provide evidence that commonly held intuitions when designing quantum circuits can be misleading. In particular we show that: a) reducing the T-count can increase the total depth; b) it may be beneficial to trade CNOTs for measurements in NISQ circuits; c) measurement-based uncomputation of relative phase Toffoli ancillae can make up to 30% of a circuits depth; d) area and volume cost metrics can misreport the resource analysis. Our findings assume that qubits are and will remain a very scarce resource. The results are applicable for both NISQ and QECC protected circuits. Our method uses multiple ways of decomposing Toffoli gates into Clifford+T gates. We illustrate our method on addition and multiplication circuits using ripple-carry. As a byproduct result we show systematically that for a practically significant range of circuit widths, ripple-carry addition circuits are more resource efficient than the carry-lookahead addition ones. The methods and circuits were implemented in the open-source QUANTIFY software.
Current quantum computer designs will not scale. To scale beyond small prototypes, quantum architectures will likely adopt a modular approach with clusters of tightly connected quantum bits and sparser connections between clusters. We exploit this clustering and the statically-known control flow of quantum programs to create tractable partitioning heuristics which map quantum circuits to modular physical machines one time slice at a time. Specifically, we create optimized mappings for each time slice, accounting for the cost to move data from the previous time slice and using a tunable lookahead scheme to reduce the cost to move to future time slices. We compare our approach to a traditional statically-mapped, owner-computes model. Our results show strict improvement over the static mapping baseline. We reduce the non-local communication overhead by 89.8% in the best case and by 60.9% on average. Our techniques, unlike many exact solver methods, are computationally tractable.
We review some of the features of the ProjectQ software framework and quantify their impact on the resulting circuits. The concise high-level language facilitates implementing even complex algorithms in a very time-efficient manner while, at the same time, providing the compiler with additional information for optimization through code annotation - so-called meta-instructions. We investigate the impact of these annotations for the example of Shors algorithm in terms of logical gate counts. Furthermore, we analyze the effect of different intermediate gate sets for optimization and how the dimensions of the resulting circuit depend on a smart choice thereof. Finally, we demonstrate the benefits of a modular compilation framework by implementing mapping procedures for one- and two-dimensional nearest neighbor architectures which we then compare in terms of overhead for different problem sizes.
We propose and demonstrate a modular architecture for reconfigurable on-chip linear-optical circuits. Each module contains 10 independent phase-controlled Mach-Zehnder interferometers; several such modules can be connected to each other to build large reconfigurable interferometers. With this architecture, large interferometers are easier to build and characterize than with traditional, bespoke, monolithic designs. We demonstrate our approach by fabricating three modules in the form of UV-written silica-on-silicon chips. We characterize these chips, connect them to each other, and implement a wide range of linear optical transformations. We envisage that this architecture will enable many future experiments in quantum optics.
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