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Register a new userHigh-performance ferroelectric memory based on fully patterned tunnel junctions
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In tunnel junctions with ferroelectric barriers, switching the polarization direction modifies the electrostatic potential profile and the associated average tunnel barrier height. This results in strong changes of the tunnel transmission and associated resistance. The information readout in ferroelectric tunnel junctions (FTJs) is thus resistive and non-destructive, which is an advantage compared to the case of conventional ferroelectric memories (FeRAMs). Initially, endurance limitation (i.e. fatigue) was the main factor hampering the industrialization of FeRAMs. Systematic investigations of switching dynamics for various ferroelectric and electrode materials have resolved this issue, with endurance now reaching $10^{14}$ cycles. Here we investigate data retention and endurance in fully patterned submicron Co/BiFeO$_3$/Ca$_{0.96}$Ce$_{0.04}$MnO$_3$ FTJs. We report good reproducibility with high resistance contrasts and extend the maximum reported endurance of FTJs by three orders of magnitude ($4times10^6$ cycles). Our results indicate that here fatigue is not limited by a decrease of the polarization or an increase of the leakage but rather by domain wall pinning. We propose directions to access extreme and intermediate resistance states more reliably and further strengthen the potential of FTJs for non-volatile memory applications.
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Silicon ferroelectric field-effect transistors (FeFETs) with low-k interfacial layer (IL) between ferroelectric gate stack and silicon channel suffers from high write voltage, limited write endurance and large read-after-write latency due to early IL breakdown and charge trapping and detrapping at the interface. We demonstrate low voltage, high speed memory operation with high write endurance using an IL-free back-end-of-line (BEOL) compatible FeFET. We fabricate IL-free FeFETs with 28nm channel length and 126nm width under a thermal budget <400C by integrating 5nm thick Hf0.5Zr0.5O2 gate stack with amorphous Indium Tungsten Oxide (IWO) semiconductor channel. We report 1.2V memory window and read current window of 10^5 for program and erase, write latency of 20ns with +/-2V write pulses, read-after-write latency <200ns, write endurance cycles exceeding 5x10^10 and 2-bit/cell programming capability. Array-level analysis establishes IL-free BEOL FeFET as a promising candidate for logic-compatible high-performance on-chip buffer memory and multi-bit weight cell for compute-in-memory accelerators.
We report on the fabrication of organic multiferroic tunnel junction (OMFTJ) based on an organic barrier of Poly(vinylidene fluoride) (PVDF):Fe3O4 nanocomposite. By adding Fe3O4 nanoparticles into the PVDF barrier, we found that the ferroelectric properties of the OMFTJ are considerably improved compared to that with pure PVDF barrier. It can lead to a tunneling electroresistance (TER) of about 450% at 10K and 100% at room temperature (RT), which is much higher than that of the pure PVDF based device (70% at 10K and 7% at RT). OMFTJs based on the PVDF:Fe3O4 nanocomposite could open new functionalities in smart multiferroic devices via the interplay of the magnetism of nanoparticle with the ferroelectricity of the organic barrier.
When biased at a voltage just below a superconductors energy gap, a tunnel junction between this superconductor and a normal metal cools the latter. While the study of such devices has long been focussed to structures of submicron size and consequently cooling power in the picoWatt range, we have led a thorough study of devices with a large cooling power up to the nanoWatt range. Here we describe how their performance can be optimized by using a quasi-particle drain and tuning the cooling junctions tunnel barrier.
Using a simple quantum-mechanical model, we explore a tunneling anisotropic magnetoresistance (TAMR) effect in ferroelectric tunnel junctions (FTJs) with a ferromagnetic electrode and a ferroelectric barrier layer, which spontaneous polarization gives rise to the Rashba and Dresselhaus spin-orbit coupling (SOC). For realistic parameters of the model, we predict sizable TAMR measurable experimentally. For asymmetric FTJs, which electrodes have different work functions, the built-in electric field affects the SOC parameters and leads to TAMR dependent on ferroelectric polarization direction. The SOC change with polarization switching affects tunneling conductance, revealing a new mechanism of tunneling electroresistance (TER). These results demonstrate new functionalities of FTJs which can be explored experimentally and used in electronic devices.
In this paper, a theoretical approach, comprising the non-equilibrium Greens function method for electronic transport and Landau-Khalatnikov equation for electric polarization dynamics, is presented to describe polarization-dependent tunneling electroresistance (TER) in ferroelectric tunnel junctions. Using appropriate contact, interface, and ferroelectric parameters, measured current-voltage characteristic curves in both inorganic (Co/BaTiO$_{3}$/La$_{0.67}$Sr$_{0.33}$MnO$_{3}$) and organic (Au/PVDF/W) ferroelectric tunnel junctions can be well described by the proposed approach. Furthermore, under this theoretical framework, the controversy of opposite TER signs observed experimentally by different groups in Co/BaTiO$_{3}$/La$_{0.67}$Sr$_{0.33}$MnO$_{3}$ systems is addressed by considering the interface termination effects using the effective contact ratio, defined through the effective screening length and dielectric response at the metal/ferroelectric interfaces. Finally, our approach is extended to investigate the role of a CoO$_{x}$ buffer layer at the Co/BaTiO$_{3}$ interface in a ferroelectric tunnel memristor. It is shown that, to have a significant memristor behavior, not only the interface oxygen vacancies but also the CoO$_{x}$ layer thickness may vary with the applied bias.
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