Subscribe to the gold package and get unlimited access to Shamra Academy
Register a new userA Fast Improved Fat Tree Encoder for Wave Union TDC in an FPGA
89
0
0.0
(
0
)
Ask ChatGPT about the research
No Arabic abstract
Up to the present, the wave union method can achieve the best timing performance in FPGA based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code (NTH2B) encoding process should be finished within just one system clock cycle. So the implementation of the NTH2B encoder is quite challenging considering the high speed requirement. Besides, the high resolution wave union TDC also demands the encoder to convert an ultra-wide input code to a binary code. We present a fast improved fat tree encoder (IFTE) to fulfill such requirements, in which bubble error suppression is also integrated. With this encoder scheme, a wave union TDC with 7.7 ps RMS and 3.8 ps effective bin size was implemented in an FPGA from Xilinx Virtex 5 family. An encoding time of 8.33 ns was achieved for a 276-bit non-thermometer code to a 9-bit binary code conversion. We conducted a series of tests on the oscillating period of the wave union launcher, as well as the overall performance of the TDC; test results indicate that the IFTE works well. In fact, in the implementation of this encoder, no manual routing or special constrains were required; therefore, this IFTE structure could also be further applied in other delay chain based FPGA TDCs.
rate research
Read More
A high precision and high resolution time-to-digital converter (TDC) implemented in a 40 nm fabrication process Virtex-6 FPGA is presented in this paper. The multi-chain measurements averaging architecture is used to overcome the resolution limitation determined by intrinsic cell delay of the plain single tapped-delay chain. The resolution and precision are both improved with this architecture. In such a TDC, the input signal is connected to multiple tapped-delay chains simultaneously (the chain number is M), and there is a fixed delay cell between every two adjacent chains. Each tapped-delay chain is just a plain TDC and should generate a TDC time for a hit input signal, so totally M TDC time values should be got for a hit signal. After averaging, the final TDC time is obtained. A TDC with 3 ps resolution (i.e. bin size) and 6.5 ps precision (i.e. RMS) has been implemented using 8 parallel tapped-delay chains. Meanwhile the plain TDC with single tapped-delay chain yields 24 ps resolution and 18 ps precision.
Time-of-flight (tof) techniques are standard techniques in high energy physics to determine particles propagation directions. Since particles velocities are generally close to c, the speed of light, and detectors typical dimensions at the meter level, the state-of-the-art tof techniques should reach sub-nanosecond timing resolution. Among the various techniques already available, the recently developed ring oscillator TDC ones, implemented in low cost FPGA, feature a very interesting figure of merit since a very good timing performance may be achieved with limited processing ressources. This issue is relevant for applications where unmanned sensors should have the lowest possible power consumption. Actually this article describes in details the application of this kind of tof technique to muon tomography of geological bodies. Muon tomography aims at measuring density variations and absolute densities through the detection of atmospheric muons fluxs attenuation, due to the presence of matter. When the measured fluxes become very low, an identified source of noise comes from backwards propagating particles hitting the detector in a direction pointing to the geological body. The separation between through-going and backward-going particles, on the basis of the tof information is therefore a key parameter for the tomography analysis and subsequent previsions.
We have developed a completely new type of general-purpose CCD data acquisition system which enables one to drive any type of CCD using any type of clocking mode. A CCD driver system widely used before consisted of an analog multiplexer (MPX), a digital-to-analog converter (DAC), and an operational amplifier. A DAC is used to determine high and low voltage levels and the MPX selects each voltage level using a TTL clock. In this kind of driver board, it is difficult to reduce the noise caused by a short of high and low level in MPX and also to select many kinds of different voltage levels. Recent developments in semiconductor IC enable us to use a very fast sampling ($sim$ 10MHz) DAC with low cost. We thus develop the new driver system using a fast DAC in order to determine both the voltage level of the clock and the clocking timing. We use FPGA (Field Programmable Gate Array) to control the DAC. We have constructed the data acquisition system and found that the CCD functions well with our new system. The energy resolution of Mn K$alpha$ has a full-width at half-maximum of $simeq$ 150 eV and the readout noise of our system is $simeq$ 8 e$^-$.
In a previous work we have demonstrated the feasibility of high-frame-rate, fast-neutron radiography of generic air-water two-phase flows in a 1.5 cm thick, rectangular flow channel. The experiments have been carried out at the high-intensity, white-beam facility of the Physikalisch-Technische Bundesanstalt, Germany, using an multi-frame, time-resolved detector developed for fast neutron resonance radiography. The results were however not fully optimal and therefore we have decided to modify the detector and optimize it for the given application, which is described in the present work. Furthermore, we managed to improve the image post-processing methodology and the noise suppression. Using the tailored detector and the improved post-processing significant increase in the image quality and an order of magnitude lower exposure times, down to 3.33 ms, have been achieved with minimized motion artifacts. Similar to the previous study, different two-phase flow regimes such as bubbly slug and churn flows have been examined. The enhanced imaging quality enables an improved prediction of two-phase flow parameters like the instantaneous volumetric gas fraction, bubble size and bubble velocities. Instantaneous velocity fields around the gas enclosures can also be more robustly predicted using optical flow methods as previously.
We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O(100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system.
Log in to be able to interact and post comments
comments
Fetching comments
Sign in to be able to follow your search criteria
