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Interface Trap Density Metrology of state-of-the-art undoped Si n-FinFETs

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 Publication date 2010
  fields Physics
and research's language is English




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The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed structures. We present the first set of methods that allow direct estimation of Dit in state-of-the-art FinFETs, addressing a critical industry need.



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Ultra-scaled FinFET transistors bear unique fingerprint-like device-to-device differences attributed to random single impurities. This paper describes how, through correlation of experimental data with multimillion atom tight-binding simulations using the NEMO 3-D code, it is possible to identify the impuritys chemical species and determine their concentration, local electric field and depth below the Si/SiO$_{mathrm{2}}$ interface. The ability to model the excited states rather than just the ground state is the critical component of the analysis and allows the demonstration of a new approach to atomistic impurity metrology.
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