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Register a new userTestability of Reversible Iterative Logic Arrays
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Added by
Avik Chakraborty
Publication date
2020
fields
Informatics Engineering
and research's language is
English
Authors
Avik Chakraborty
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Iterative Logic Arrays (ILAs) are ideal as VLSI sub-systems because of their regular structure and its close resemblance with FPGAs (Field Programmable Gate Arrays). Reversible circuits are of interest in the design of very low power circuits where energy loss implied by high frequency switching is not of much consideration. Reversibility is essential for Quantum Computing. This paper examines the testability of Reversible Iterative Logic Arrays (ILAs) composed of reversible k-CNOT gates. For certain ILAs it is possible to find a test set whose size remains constant irrespective of the size of the ILA, while for others it varies with array size. Former type of ILAs is known as Constant-Testable, i.e. C-Testable. It has been shown that Reversible Logic Arrays are C-Testable and size of test set is equal to number of entries in cells truth table implying that the reversible ILAs are also Optimal-Testable, i.e. O-Testable. Uniform-Testability, i.e. U-Testability has been defined and Reversible Heterogeneous ILAs have been characterized as U-Testable. The test generation problem has been shown to be related to certain properties of cycles in a set of graphs derived from cell truth table. By careful analysis of these cycles an efficient test generation technique that can be easily converted to an ATPG program has been presented for both 1-D and 2D ILAs. The same algorithms can be easily extended for n-Dimensional Reversible ILAs.
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Reversible circuits find applications in many areas of Computer Science including Quantum Computation. This paper examines the testability of an important subclass of reversible logic circuits that are composed of k-wire controlled NOT (k-CNOT with k >/- 1) gates. A reversible k-CNOT gate can be implemented using an irreversible k-input AND gate and an EXOR gate. A reversible k-CNOT circuit where each k-CNOT gate is realized using irreversible k-input AND and EXOR gate, has been considered. One of the most commonly used Single Bridging Fault model (both wired-AND and wired-OR) has been assumed to be type of fault for such circuits. It has been shown that an (n+p)-input AND-EXOR based reversible logic circuit with p observable outputs, can be tested for single bridging faults (SBF) using (3n + lefthalfcap log2p righthalfcap + 2) tests.
In recent years reversible logic has been considered as an important issue for designing low power digital circuits. It has voluminous applications in the present rising nanotechnology such as DNA computing, Quantum Computing, low power VLSI and quantum dot automata. In this paper we have proposed optimized design of reversible sequential circuits in terms of number of gates, delay and hardware complexity. We have designed the latches with a new reversible gate and reduced the required number of gates, garbage outputs, and delay and hardware complexity. As the number of gates and garbage outputs increase the complexity of reversible circuits, this design will significantly enhance the performance. We have proposed reversible D-latch and JK latch which are better than the existing designs available in literature.
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiting factor. Reversible computing can potentially require arbitrarily small amounts of energy. Recently several nano-scale devices which have the potential to scale, and which naturally perform reversible logic, have emerged. This paper addresses several fundamental issues that need to be addressed before any nano-scale reversible computing systems can be realized, including reliability and performance trade-offs and architecture optimization. Many nano-scale devices will be limited to only near neighbor interactions, requiring careful optimization of circuits. We provide efficient fault-tolerant (FT) circuits when restricted to both 2D and 1D. Finally, we compute bounds on the entropy (and hence, heat) generated by our FT circuits and provide quantitative estimates on how large can we make our circuits before we lose any advantage over irreversible computing.
Computational reversibility is necessary for quantum computation and inspires the development of computing systems in which information carriers are conserved as they flow through a circuit. While conservative logic provides an exciting vision for reversible computing with no energy dissipation, the large dimensions of information carriers in previous realizations detract from the system efficiency, and nanoscale conservative logic remains elusive. We therefore propose a non-volatile reversible computing system in which the information carriers are magnetic skyrmions, topologically-stable magnetic whirls. These nanoscale quasiparticles interact with one another via the spin-Hall and skyrmion-Hall effects as they propagate through ferromagnetic nanowires structured to form cascaded conservative logic gates. These logic gates can be directly cascaded in large-scale systems that perform complex logic functions, with signal integrity provided by clocked synchronization structures. The feasibility of the proposed system is demonstrated through micromagnetic simulations of Boolean logic gates, a Fredkin gate, and a cascaded full adder. As skyrmions can be transported in a pipelined and non-volatile manner at room temperature without the motion of any physical particles, this skyrmion logic system has the potential to deliver scalable high-speed low-power reversible Boolean and quantum computing.
In this paper, we present DATC Robust Design Flow (RDF) from logic synthesis to detailed routing. Our goals are 1) to provide an open-source academic design flow from logic synthesis to detailed routing based on existing contest results, 2) to construct a database for design benchmarks and point tool libraries, and 3) to interact with industrial designs by using industrial standard design input/output formats. We also demonstrate RDF in a scalable cloud infrastructure. Design methodology and cross-stage optimization research can be conducted via RDF.
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