A high accuracy and high sensitivity system architecture is proposed for the read-out circuit of electrical impedance tomography system-on-chip. The switched ratiometric technique is applied in the proposed architecture. The proposed system architecture minimizes the device noise by processing signals from both read-out electrodes and the stimulus. The quantized signals are post-processed in the digital processing unit for proper signal demodulation and impedance ratio calculation. Our proposed architecture improves the sensitivity of the read-out circuit, cancels out the gain fluctuations in the system, and overcomes the effects of motion artifacts on measurements.
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