A comprehensive study of drain current dispersion effects in $beta$-Ga$_2$O$_3$ FETs has been done using DC, pulsed and RF measurements. Both virtual gate effect in the gate-drain access region and interface traps under the gate are most plausible explanations for the experimentally observed pulsed current dispersion and high temperature threshold voltage shift respectively. Unpassivated devices show significant current dispersion between DC and pulsed IV response due to gate lag effect characterized by time constants in the range of 400~$mu s$ to 600~$mu s$. An activation energy of 99~$meV$ is estimated from temperature dependent Arrhenius plots. A variable range hopping based slow transport in conjunction with the observed shallow trap level is attributed to the observed slow transient response of drain current with respect to time. Reactive ion etching step during the device fabrication is most likely responsible for introducing the traps. Effect of traps can be minimized by using surface passivation layers, in this case, Silicon Nitride which shows significant improvement in the current dispersion and RF cutoff frequency. This work demonstrates the detrimental effect the traps can have on the current dispersion which significantly limits the high frequency operation of the device.
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