We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $mu$-TPCs for directional dark matter searches. Low-noise performance and wide dynamic range are two requirements for reading out the signals induced on the TPC readout channels. One of the development objectives is to establish the analog processing circuits under low temperature operation, which are designed on function block basis as reusable IPs (Intellectual Properties). The newly developed ASIC was implemented in the Silterra 180~nm CMOS technology and has 16 readout channels. We carried out the performance test at room temperature and the results showed an equivalent noise charge of 2695$pm$71~e$^-$ (rms) with a detector capacitance of 300~pF. The dynamic range was measured to be 20--100~fC in the low-gain mode and 200--1600~fC in the high-gain mode within 10% integral nonlinearity at room temperature. We also tested the performance at the liquid-Ar temperature and found a deterioration of the noise level with a longer shaper time. Based on these results, we also discuss a unique simulation methodology for future cold-electronics development. This method can be applicable to design the electronics used at low temperature.
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