The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data in the Micromegas detector of the ATLAS New Small Wheel (NSW) upgrade. The ART signals are generated by the front end ASIC, named VMM chip, to indicate the address of the first above-threshold event. A custom ASIC (ART ASIC) is designed to receive the ART signals from the VMM chip and do the hit-selection processing. Processed data from ART ASIC will be transmitted out of the NSW detector through GBTx serializer, VTTx optical transmitter module and fiber optical links. The ART signal is critical for the ATLAS experiment trigger selection thus the functionality and stability of the ADDC is very important. To ensure extensive testing of the ADDC, an FMC based testing platform and special firmware/software are developed. This test platform works with the commercial Xilinx VC707 FPGA develop kit, even without the other electronics of the NSW it can test all the functionality of the ADDC and also long term stability. This paper will introduce the design, testing procedure and results from the ADDC and the FMC testing platform.
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