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Spins based in silicon provide one of the most promising architectures for quantum computing. A scalable design for silicon-germanium quantum dot qubits is presented. The design incorporates vertical and lateral tunneling. Simulations of a four-qubit array suggest that the design will enable single electron occupation of each dot of a many-dot array. Performing two-qubit operations has negligible effect on other qubits in the array. Simulation results are used to translate error correction requirements into specifications for gate-voltage control electronics. This translation is a necessary link between error correction theory and device physics.
Spins based in silicon provide one of the most promising architectures for quantum computing. Quantum dots are an inherently scalable technology. Here, we combine these two concepts into a workable design for a silicon-germanium quantum bit. The nove
The spin states of single electrons in gate-defined quantum dots satisfy crucial requirements for a practical quantum computer. These include extremely long coherence times, high-fidelity quantum operation, and the ability to shuttle electrons as a m
A two-qubit controlled-NOT (CNOT) gate, realized by a controlled-phase (C-phase) gate combined with single-qubit gates, has been experimentally implemented recently for quantum-dot spin qubits in isotopically enriched silicon, a promising solid-state
Electrons and holes confined in quantum dots define an excellent building block for quantum emergence, simulation, and computation. In order for quantum electronics to become practical, large numbers of quantum dots will be required, necessitating th
Quantum gates between spin qubits can be implemented leveraging the natural Heisenberg exchange interaction between two electrons in contact with each other. This interaction is controllable by electrically tailoring the overlap between electronic wa