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We report a new approach to integrating high-k{appa} dielectrics in both bottom- and top-gated MoS2 field-effect transistors (FETs) through thermal oxidation and mechanical assembly of layered twodimensional (2D) TaS2. Combined X-ray photoelectron spectroscopy (XPS), optical microscopy, atomic force microscopy (AFM), and capacitance-voltage (C-V) measurements confirm that multilayer TaS2 flakes can be uniformly transformed to Ta2O5 with a high dielectric constant of ~ 15.5 via thermal oxidation, while preserving the geometry and ultra-smooth surfaces of 2D TMDs. Top-gated MoS2 FETs fabricated using the thermally oxidized Ta2O5 as gate dielectric demonstrate a high current on/off ratio approaching 106, a subthreshold swing (SS) down to 61 mV/dec, and a field-effect mobility exceeding 60 cm2V-1 s-1 at room temperature, indicating high dielectric quality and low interface trap density.
We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique. Top gates were then defined aligned to the bott
We report the development of nanowire field-effect transistors featuring an ultra-thin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high
Electrical characterization of few-layer MoS2 based field effect transistors with Ti/Au electrodes is performed in the vacuum chamber of a scanning electron microscope in order to study the effects of electron beam irradiation on the transport proper
Non-volatile memory devices have been limited to flash architectures that are complex devices. Here, we present a unique photomemory effect in MoS$_2$ transistors. The photomemory is based on a photodoping effect - a controlled way of manipulating th
For the first time, n-type few-layer MoS2 field-effect transistors with graphene/Ti as the hetero-contacts have been fabricated, showing more than 160 mA/mm drain current at 1 {mu}m gate length with an on-off current ratio of 107. The enhanced electr