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2D material based tunnel FETs are among the most promising candidates for low power electronics applications since they offer ultimate gate control and high current drives that are achievable through small tunneling distances during the device operation. The ideal device is characterized by a minimized tunneling distance. However, devices with the thinnest possible body do not necessarily provide the best performance. For example, reducing the channel thickness increases the depletion width in the source which can be a significant part of the total tunneling distance. Hence, it is important to determine the optimum channel thickness for each channel material individually. In this work, we study the optimum channel thickness for three channel materials: WSe$_{2}$, Black Phosphorus (BP), and InAs using full-band self-consistent quantum transport simulations. To identify the ideal channel thickness for each material at a specific doping density, a new analytic model is proposed and benchmarked against the numerical simulations.
We report on detailed room temperature and low temperature transport properties of double-gate Si MOSFETs with the Si well thickness in the range 7-17 nm. The devices were fabricated on silicon-on-insulator wafers utilizing wafer bonding, which enabl
We demonstrate a selectively emitting optical Fabry-Perot resonator based on a few-nm-thin continuous metallic titanium nitride film, separated by a dielectric spacer from an optically thick titanium nitride back-reflector, which exhibits excellent s
Here, we propose a method to determine the thickness of the most common transition metal dichalcogenides (TMDCs) placed on the surface of transparent stamps, used for the deterministic placement of two-dimensional materials, by analyzing the red, gre
We present the results of atomic-force-microscopy-based friction measurements on Re-doped molybdenum disulfide (MoS2). In stark contrast to the seemingly universal observation of decreasing friction with increasing number of layers on two-dimensional
Triple heterojunction (THJ) TFETs have been proposed to resolve the low ON-current challenge of TFETs. However, the design space for THJ-TFETs is limited by fabrication challenges with respect to device dimensions and material interfaces. This work s