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تسجيل مستخدم جديدChecking the error correction strength of arbitrary surface code logical gates
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Topologically quantum error corrected logical gates are complex. Chains of errors can form in space and time and diagonally in spacetime. It is highly nontrivial to determine whether a given logical gate is free of low weight combinations of errors leading to failure. We report a new tool Nestcheck capable of analyzing an arbitrary topological computation and determining the minimum number of errors required to cause failure.
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We realize a suite of logical operations on a distance-two logical qubit stabilized using repeated error detection cycles. Logical operations include initialization into arbitrary states, measurement in the cardinal bases of the Bloch sphere, and a u
niversal set of single-qubit gates. For each type of operation, we observe higher performance for fault-tolerant variants over non-fault-tolerant variants, and quantify the difference through detailed characterization. In particular, we demonstrate process tomography of logical gates, using the notion of a logical Pauli transfer matrix. This integration of high-fidelity logical operations with a scalable scheme for repeated stabilization is a milestone on the road to quantum error correction with higher-distance superconducting surface codes.
The yield of physical qubits fabricated in the laboratory is much lower than that of classical transistors in production semiconductor fabrication. Actual implementations of quantum computers will be susceptible to loss in the form of physically faul
ty qubits. Though these physical faults must negatively affect the computation, we can deal with them by adapting error correction schemes. In this paper We have simulated statically placed single-fault lattices and lattices with randomly placed faults at functional qubit yields of 80%, 90% and 95%, showing practical performance of a defective surface code by employing actual circuit constructions and realistic errors on every gate, including identity gates. We extend Stace et al.s superplaquettes solution against dynamic losses for the surface code to handle static losses such as physically faulty qubits. The single-fault analysis shows that a static loss at the periphery of the lattice has less negative effect than a static loss at the center. The randomly-faulty analysis shows that 95% yield is good enough to build a large scale quantum computer. The local gate error rate threshold is $sim 0.3%$, and a code distance of seven suppresses the residual error rate below the original error rate at $p=0.1%$. 90% yield is also good enough when we discard badly fabricated quantum computation chips, while 80% yield does not show enough error suppression even when discarding 90% of the chips. We evaluated several metrics for predicting chip performance, and found that the average of the product of the number of data qubits and the cycle time of a stabilizer measurement of stabilizers gave the strongest correlation with post-correction residual error rates. Our analysis will help with selecting usable quantum computation chips from among the pool of all fabricated chips.
Fault-tolerant quantum computing demands many qubits with long lifetimes to conduct accurate quantum gate operations. However, external noise limits the computing time of physical qubits. Quantum error correction codes may extend such limits, but imp
erfect gate operations introduce errors to the correction procedure as well. The additional gate operations required due to the physical layout of qubits exacerbate the situation. Here, we use density-matrix simulations to investigate the performance change of logical qubits according to quantum error correction codes and qubit layouts and the expected performance of logical qubits with gate operation time and gate error rates. Considering current qubit technology, the small quantum error correction codes are chosen. Assuming 0.1% gate error probability, a logical qubit encoded by a 5-qubit quantum error correction code is expected to have a fidelity 0.25 higher than its physical counterpart.
Bosonic quantum error correction is a viable option for realizing error-corrected quantum information processing in continuous-variable bosonic systems. Various single-mode bosonic quantum error-correcting codes such as cat, binomial, and GKP codes h
ave been implemented experimentally in circuit QED and trapped ion systems. Moreover, there have been many theoretical proposals to scale up such single-mode bosonic codes to realize large-scale fault-tolerant quantum computation. Here, we consider the concatenation of the single-mode GKP code with the surface code, namely, the surface-GKP code. In particular, we thoroughly investigate the performance of the surface-GKP code by assuming realistic GKP states with a finite squeezing and noisy circuit elements due to photon losses. By using a minimum-weight perfect matching decoding algorithm on a 3D space-time graph, we show that fault-tolerant quantum error correction is possible with the surface-GKP code if the squeezing of the GKP states is higher than 11.2dB in the case where the GKP states are the only noisy elements. We also show that the squeezing threshold changes to 18:6dB when both the GKP states and circuit elements are comparably noisy. At this threshold, each circuit component fails with probability 0.69%. Finally, if the GKP states are noiseless, fault-tolerant quantum error correction with the surface-GKP code is possible if each circuit element fails with probability less than 0.81%. We stress that our decoding scheme uses the additional information from GKP-stabilizer measurements and we provide a simple method to compute renormalized edge weights of the matching graphs. Furthermore, our noise model is general as it includes full circuit-level noise.
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cise value of the threshold depends on the noise model, measurement circuits, and decoding algorithm. We observe thresholds between 0.502(1)% and 1.140(1)% per gate, values which are generally lower than previous estimates.
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