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Register a new userA massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process
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A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analytical model of linearity. The model allowed us to understand the source of the performance superiority (in terms of linearity) of our design and to predict further improvements. The oscillator is integrated in a event-by-event self-calibration system that allows avoiding any PLL-based synchronization. For this reason and for the compactness and simplicity of the architecture, the proposed TDC is suitable for applications in which a large number of converters and a massive parallelization are required such as High-Energy Physics and medical imaging detector systems. A test chip for the TDC has been fabricated and tested. The TDC shows a DNL$leq$1.3 LSB, an INL$leq$2 LSB and a single-shot precision of 19.5 ps (0.58 LSB). The chip dissipates a power of 5.4 mW overall.
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Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of off-the-shelf TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition systems and the interface to the online FARM of KLOE-2.
We present some aspects of photon counting to study scintillators at low temperatures. A time-to-digital converter (TDC) had been configured to acquire several-minute-long streams of data, simplifying the multiple photon counting coincidence technique. Results in terms of light yield and time structure of a ZnWO4 scintillator are comparable to those obtained with a fast digitizer. Streaming data also provides flexibility in analyzing the data, in terms of coincidence window between the channels, and acquisition window of individual channels. We discuss the effect of changing these parameters, and use them to confirm low-energy features in the spectra of the number of detected photons, such as the 60 keV line from 241Am in the ZnWO4 sample. We lastly use the TDC to study the transmission of the optical cryostat employed in these studies at various temperatures.
Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful to cope with the changes in the experimental conditions. Recent FPGAs make it possible to implement TDCs with a time resolution less than 10 ps. On the other hand, various drift chambers require a time resolution of O(0.1) ns, and a simple and easy-to-implement TDC is useful for a robust operation. Herein an eight-channel TDC with a variable bin size down to 0.28 ns is implemented in a Xilinx Kintex-7 FPGA and tested. The TDC is based on a multisampling scheme with quad phase clocks synchronised with an external reference clock. Calibration of the bin size is unnecessary if a stable reference clock is available, which is common in high-energy physics experiments. Depending on the channel, the standard deviation of the differential nonlinearity for a 0.28 ns bin size is 0.13-0.31. The performance has a negligible dependence on the temperature. The power consumption and the potential to extend the number of channels are also discussed.
In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a Time to Digital Converter (TDC) with 625 ps resolution (LSB) along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. We will describe briefly the architecture of the TDC and of the Data AcQuisition (DAQ) system. Some more details will be provided about the zero-suppression algorithm used to reduce the data throughput.
A high-precision charge measurement can be achieved by the area integration of a digitized quasi-Gaussian signal after the signal passes through the shaper and analog-to-digital converter (ADC). The charge measurement contains an error due to the uncertainty of the first sampled point of a signal waveform. To reduce the error, we employ a time-to-digital converter (TDC) to measure the uncertainty precisely, and we design correction algorithms to improve the resolution of the charge measurement. This work includes analysis and simulations of the proposed algorithms and implementation of them in an FPGA device. Besides, the tests are also conducted to evaluate the performance of the correction method. Test results indicate that the resolution of the charge measurement is successfully improved from 0.231% to 0.126% by using a signal from the shaping circuit (with the amplitude of 2 V, and leading and trailing edges of about 80 ns and 280 ns, respectively) digitized at the sampling rate of 62.5 Msps.
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