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Register a new userCMOS-Free Multilayer Perceptron Enabled by Four-Terminal MTJ Device
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Neuromorphic computing promises revolutionary improvements over conventional systems for applications that process unstructured information. To fully realize this potential, neuromorphic systems should exploit the biomimetic behavior of emerging nanodevices. In particular, exceptional opportunities are provided by the non-volatility and analog capabilities of spintronic devices. While spintronic devices have previously been proposed that emulate neurons and synapses, complementary metal-oxide-semiconductor (CMOS) devices are required to implement multilayer spintronic perceptron crossbars. This work therefore proposes a new spintronic neuron that enables purely spintronic multilayer perceptrons, eliminating the need for CMOS circuitry and simplifying fabrication.
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Controlled atomic scale fabrication of functional devices is one of the holy grails of nanotechnology. The most promising class of techniques that enable deterministic nanodevice fabrication are based on scanning probe patterning or surface assembly. However, this typically involves a complex process flow, stringent requirements for an ultra high vacuum environment, long fabrication times and, consequently, limited throughput and device yield. Here, a device platform is developed that overcomes these limitations by integrating scanning probe based dopant device fabrication with a CMOS-compatible process flow. Silicon on insulator substrates are used featuring a reconstructed Si(001):H surface that is protected by a capping chip and has pre-implanted contacts ready for scanning tunneling microscope (STM) patterning. Processing in ultra-high vacuum is thus reduced to only a few critical steps which minimizes the complexity, time and effort required for fabrication of the nanoscale dopant devices. Subsequent reintegration of the samples into the CMOS process flow not only simplifies the post-processing but also opens the door to successful application of STM based dopant devices as a building block in more complex device architectures. Full functionality of this approach is demonstrated with magnetotransport measurements on degenerately doped STM patterned Si:P nanowires up to room temperature.
Neuromorphic computing systems overcome the limitations of traditional von Neumann computing architectures. These computing systems can be further improved upon by using emerging technologies that are more efficient than CMOS for neural computation. Recent research has demonstrated memristors and spintronic devices in various neural network designs boost efficiency and speed. This paper presents a biologically inspired fully spintronic neuron used in a fully spintronic Hopfield RNN. The network is used to solve tasks, and the results are compared against those of current Hopfield neuromorphic architectures which use emerging technologies.
Complementary metal oxide semiconductor (CMOS) devices display volatile characteristics, and are not well suited for analog applications such as neuromorphic computing. Spintronic devices, on the other hand, exhibit both non-volatile and analog features, which are well-suited to neuromorphic computing. Consequently, these novel devices are at the forefront of beyond-CMOS artificial intelligence applications. However, a large quantity of these artificial neuromorphic devices still require the use of CMOS, which decreases the efficiency of the system. To resolve this, we have previously proposed a number of artificial neurons and synapses that do not require CMOS for operation. Although these devices are a significant improvement over previous renditions, their ability to enable neural network learning and recognition is limited by their intrinsic activation functions. This work proposes modifications to these spintronic neurons that enable configuration of the activation functions through control of the shape of a magnetic domain wall track. Linear and sigmoidal activation functions are demonstrated in this work, which can be extended through a similar approach to enable a wide variety of activation functions.
We demonsrtate electrical spin injection and detection in $n$-type Ge ($n$-Ge) at room temperature using four-terminal nonlocal spin-valve and Hanle-effect measurements in lateral spin-valve (LSV) devices with Heusler-alloy Schottky tunnel contacts. The spin diffusion length ($lambda$$_{rm Ge}$) of the Ge layer used ($n sim$ 1 $times$ 10$^{19}$ cm$^{-3}$) at 296 K is estimated to be $sim$ 0.44 $pm$ 0.02 $mu$m. Room-temperature spin signals can be observed reproducibly at the low bias voltage range ($le$ 0.7 V) for LSVs with relatively low resistance-area product ($RA$) values ($le$ 1 k$Omega$$mu$m$^{2}$). This means that the Schottky tunnel contacts used here are more suitable than ferromagnet/MgO tunnel contacts ($RA ge$ 100 k$Omega$$mu$m$^{2}$) for developing Ge spintronic applications.
We propose a heterostructure device comprised of magnets and piezoelectrics that significantly improves the delay and the energy dissipation of an all-spin logic (ASL) device. This paper studies and models the physics of the device, illustrates its operation, and benchmarks its performance using SPICE simulations. We show that the proposed device maintains low voltage operation, non-reciprocity, non-volatility, cascadability, and thermal reliability of the original ASL device. Moreover, by utilizing the deterministic switching of a magnet from the saddle point of the energy profile, the device is more efficient in terms of energy and delay and is robust to thermal fluctuations. The results of simulations show that compared to ASL devices, the proposed device achieves 21x shorter delay and 27x lower energy dissipation per bit for a 32-bit arithmetic-logic unit (ALU).
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