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Register a new userVerifying Parallel Loops with Separation Logic
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Added by
EPTCS
Publication date
2014
fields
Informatics Engineering
and research's language is
English
Authors
Stefan Blom
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This paper proposes a technique to specify and verify whether a loop can be parallelised. Our approach can be used as an additional step in a parallelising compiler to verify user annotations about loop dependences. Essentially, our technique requires each loop iteration to be specified with the locations it will read and write. From the loop iteration specifications, the loop (in)dependences can be derived. Moreover, the loop iteration specifications also reveal where synchronisation is needed in the parallelised program. The loop iteration specifications can be verified using permission-based separation logic.
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