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Register a new userA Three-dimensional simulation study of the performance of Carbon Nanotube Field Effect Transistors with doped reservoirs and realistic geometry
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In this work, we simulate the expected device performance and the scaling perspectives of Carbon nanotube Field Effect Transistors (CNT-FETs), with doped source and drain extensions. The simulations are based on the self-consistent solution of the 3D Poisson-Schroedinger equation with open boundary conditions, within the Non-Equilibrium Greens Function formalism, where arbitrary gate geometry and device architecture can be considered. The investigation of short channel effects for different gate configurations and geometry parameters shows that double gate devices offer quasi ideal subthreshold slope and DIBL without extremely thin gate dielectrics. Exploration of devices with parallel CNTs show that On currents per unit width can be significantly larger than the silicon counterpart, while high-frequency performance is very promising.
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Electronic transport in a carbon nanotube (CNT) metal-oxide-semiconductor field effect transistor (MOSFET) is simulated using the non-equilibrium Greens functions method with the account of electron-phonon scattering. For MOSFETs, ambipolar conduction is explained via phonon-assisted band-to-band (Landau-Zener) tunneling. In comparison to the ballistic case, we show that the phonon scattering shifts the onset of ambipolar conduction to more positive gate voltage (thereby increasing the off current). It is found that the subthreshold swing in ambipolar conduction can be made as steep as 40mV/decade despite the effect of phonon scattering.
We report the radio-frequency performance of carbon nanotube array transistors that have been realized through the aligned assembly of highly separated, semiconducting carbon nanotubes on a fully scalable device platform. At a gate length of 100 nm, we observe output current saturation and obtain as-measured, extrinsic current gain and power gain cut-off frequencies, respectively, of 7 GHz and 15 GHz. While the extrinsic current gain is comparable to the state-of-the-art the extrinsic power gain is improved. The de-embedded, intrinsic current gain and power gain cut-off frequencies of 153 GHz and 30 GHz are the highest values experimentally achieved to date. We analyze the consistency of DC and AC performance parameters and discuss the requirements for future applications of carbon nanotube array transistors in high-frequency electronics.
The observed performances of carbon nanotube field effect transistors are examined using first-principles quantum transport calculations. We focus on the nature and role of the electrical contact of Au and Pd electrodes to open-ended semiconducting nanotubes, allowing the chemical contact at the surface to fully develop through large-scale relaxation of the contacting atomic configuration. We present the first direct numerical evidence of Pd contacts exhibiting perfect transparency for hole injection as opposed to that of Au contacts. Their respective Schottky barrier heights, on the other hand, turn out to be fairly similar for realistic contact models. These findings are in general agreement with experimental data reported to date, and show that a Schottky contact is not merely a passive ohmic contact but actively influences the device I-V behavior.
The high-frequency transconductance and current noise of top-gated single carbon nanotube transistors have been measured and used to investigate hot electron effects in one-dimensional transistors. Results are in good agreement with a theory of 1-dimensional nano-transistor. In particular the prediction of a large transconductance correction to the Johnson-Nyquist thermal noise formula is confirmed experimentally. Experiment shows that nanotube transistors can be used as fast charge detectors for quantum coherent electronics with a resolution of $13mathrm{mu e/sqrt{Hz}}$ in the 0.2-$0.8 mathrm{GHz}$ band.
Carbon nanotube field-effect transistors (CNT FETs) have been proposed as possible building blocks for future nano-electronics. But a challenge with CNT FETs is that they appear to randomly display varying amounts of hysteresis in their transfer characteristics. The hysteresis is often attributed to charge trapping in the dielectric layer between the nanotube and the gate. This study includes 94 CNT FET samples, providing an unprecedented basis for statistics on the hysteresis seen in five different CNT-gate configurations. We find that the memory effect can be controlled by carefully designing the gate dielectric in nm-thin layers. By using atomic layer depositions (ALD) of HfO$_{2}$ and TiO$_{2}$ in a triple-layer configuration, we achieve the first CNT FETs with consistent and narrowly distributed memory effects in their transfer characteristics.
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