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Register a new userThreshold Voltage Shift in Organic Field Effect Transistors by Dipole-Monolayers on the Gate Insulator
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We demonstrate controllable shift of the threshold voltage and the turn-on voltage in pentacene thin film transistors and rubrene single crystal field effect transistors (FET) by the use of nine organosilanes with different functional groups. Prior to depositing the organic semiconductors, the organosilanes were applied to the SiO2 gate insulator from solution and form a self assembled monolayer (SAM). The observed shift of the transfer characteristics range from -2 to 50 V and can be related to the surface potential of the layer next to the transistor channel. Concomitantly the mobile charge carrier concentration at zero gate bias reaches up to 4*10^12/cm^2. In the single crystal FETs the measured transfer characteristics are also shifted, while essentially maintaining the high quality of the subthreshold swing. The shift of the transfer characteristics is governed by the built-in electric field of the SAM and can be explained using a simple energy level diagram. In the thin film devices, the subthreshold region is broadened, indicating that the SAM creates additional trap states, whose density is estimated to be of order 1*10^12/cm^2.
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The surface conductivity is measured by a four-probe technique for pentacene and rubrene single-crystals laminated on polarized and nearly unpolarized molecular monolayers with application of perpendicular electric fields. The polarization of the self-assembled monolayers (SAMs) shifts the threshold gate voltage, while maintaining a very low subthreshold swing of the single-crystal devices (0.11 V/decade). The results, excluding influences of parasitic contacts and grain boundaries, demonstrate SAM-induced nanoscale charge injection up to ~10^12 cm^-2 at the surface of the organic single crystals.
We report the development of nanowire field-effect transistors featuring an ultra-thin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally-coated nanowires, which we used to produce functional $Omega$-gate and gate-all-around structures. These give sub-threshold swings as low as 140 mV/dec and on/off ratios exceeding $10^3$ at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically-treated nanowire surfaces; a feature generally not possible with oxides produced by atomic layer deposition due to the surface `self-cleaning effect. Our results highlight the potential for parylene as an alternative ultra-thin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylenes well-established biocompatible properties.
This paper has been withdrawn by the author.
The linear band dispersion of graphenes bands near the Fermi level gives rise to its unique electronic properties, such as a giant carrier mobility, and this has triggered extensive research in applications, such as graphene field-effect transistors (GFETs). However, GFETs generally exhibit a device performance much inferior compared to the expected one. This has been attributed to a strong dependence of the electronic properties of graphene on the surrounding interfaces. Here we study the interface between a graphene channel and SiO$_{2}$, and by means of photoelectron spectromicroscopy achieve a detailed determination of the course of band alignment at the interface. Our results show that the electronic properties of graphene are modulated by a hydrophilic SiO$_{2}$ surface, but not by a hydrophobic one. By combining photoelectron spectromicroscopy with GFET transport property characterization, we demonstrate that the presence of electrical dipoles in the interface, which reflects the SiO$_{2}$ surface electrochemistry, determines the GFET device performance. A hysteresis in the resistance vs. gate voltage as a function of polarity is ascribed to a reversal of the dipole layer by the gate voltage. These data pave the way for GFET device optimization.
Bias stress degradation in conjugated polymer field-effect transistors is a fundamental problem in these disordered materials and can be traced back to interactions of the material with environmental species,1,2,3 as well as fabrication-induced defects.4,5 However, the effect of the end groups of the polymer gate dielectric and the associated dipole-induced disorder on bias stress stability has not been studied so far in high-performing n-type materials, such as N2200.6,7 In this work, the performance metrics of N2200 transistors are examined with respect to dielectrics with different end groups (Cytop-M and Cytop-S8). We hypothesize that the polar end groups would lead to increased dipole-induced disorder, and worse performance.1,9,10 The long-time annealing scheme at lower temperatures used in the paper is assumed to lead to better crystallization by allowing the crystalline domains to reorganize in the presence of the solvent.11 It is hypothesized that the higher crystallinity could narrow down the range at which energy carriers are induced and thus decrease the gate dependence of the mobility. The results show that the dielectric end groups do not influence the bias stress stability of N2200 transistors. However, long annealing times result in a dramatic improvement in bias stress stability, with the most stable devices having a mobility that is only weakly dependent on or independent of gate voltage.
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